HEMT semiconductor device and a process of forming the same

US9070705B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9070705-B2
Application numberUS-201414190839-A
CountryUS
Kind codeB2
Filing dateFeb 26, 2014
Priority dateMar 15, 2013
Publication dateJun 30, 2015
Grant dateJun 30, 2015

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A HEMT semiconductor device can include a dielectric layer that includes a silicon nitride film and an AlN film. In an embodiment, the HEMT semiconductor device can include a GaN film and an AlGaN film. In a process of forming the HEMT device, the AlN can provide an etch stop when forming an opening for a gate electrode.

First claim

Opening claim text (preview).

What is claimed is: 1. A HEMT semiconductor device comprising: a substrate having a primary surface; a GaN film overlying the primary surface of the substrate; a dielectric layer overlying the GaN film, wherein the dielectric layer includes a first silicon nitride film overlying the GaN film, and an AlN film on the first silicon nitride film; and a gate electrode disposed above the dielectric layer such that a line vertically bisecting the gate electrode intersects the first silicon nitride film and the AlN film. 2. The HEMT semiconductor device of claim 1 , wherein the HEMT semiconductor comprises a heterojunction that includes the GaN film. 3. The HEMT semiconductor device of claim 2 , the heterojunction further comprises a first AlGaN film overlying the GaN film, wherein the dielectric layer overlies the first of AlGaN film. 4. The HEMT semiconductor device of claim 3 , further comprising a source contact and a drain contact to the first AlGaN film. 5. The HEMT semiconductor device of claim 1 , wherein the gate electrode directly contacts the AlN film. 6. The HEMT semiconductor device of claim 5 , wherein the AlN film has a thickness in a range of 2 nm to 20 nm. 7. The HEMT semiconductor device of claim 1 , wherein the gate electrode directly contacts the first silicon nitride film. 8. The HEMT semiconductor device of claim 1 , further comprising a second AlGaN film, wherein the second AlGaN film is disposed between the substrate and the GaN film. 9. The HEMT semiconductor device of claim 1 , wherein the HEMT semiconductor device exhibits less gate capacitance as compared to another HEMT semiconductor device that is substantially the same except that the dielectric layer only includes the first silicon nitride film and no AlN film. 10. The HEMT semiconductor device of claim 1 , wherein the HEMT semiconductor device exhibits less threshold voltage shift as compared to another HEMT semiconductor device that is substantially the same except that the dielectric layer only includes the first silicon nitride film and no AlN film. 11. A method of forming a HEMT semiconductor device comprising: providing a substrate having a primary surface; forming a GaN film overlying the primary surface of the substrate; forming a gate dielectric layer overlying the GaN film including forming a first silicon nitride film and forming an AlN film on the first silicon nitride film; and etching an opening after forming the gate dielectric layer. 12. The method of claim 11 , further comprising forming an AlGaN film overlying the GaN film. 13. The method of claim 11 , further including forming a second silicon nitride film on the AlN film. 14. The method of claim 13 , wherein forming the dielectric layer includes forming a nitride-to-nitride bond between the first silicon nitride film and the AlN film, and forming another nitride-to-nitride bond between the AlN film and the second silicon nitride film. 15. The method of claim 13 , further comprising: forming a gate electrode within the opening extending through the second silicon nitride film and in direct contact with the AlN film. 16. The method of claim 11 , wherein forming the gate dielectric layer includes forming a nitride-to-nitride bond between the first silicon nitride film and the AlN film. 17. The method of claim 11 , wherein forming the gate dielectric layer includes oxidizing at least a portion of the AlN film. 18. The method of claim 11 , further including forming the AlGaN film on the GaN film, and forming the gate dielectric layer on the AlGaN film. 19. The method of claim 11 , further including forming an opening in the gate dielectric layer including forming the opening to extend through the AlN film by selectively etching the AlN film and stopping the etch on the first silicon nitride film, then etching the exposed portion of the first silicon nitride film to extend the opening through the first silicon nitride film. 20. A HEMT semiconductor device comprising: a substrate having a primary surface; a channel film overlying the primary surface of the substrate; a dielectric layer overlying the channel film, wherein the dielectric layer includes a first silicon nitride film overlying the channel film, and an AlN film on the first silicon nitride film; and a gate electrode disposed above and entirely spaced apart from the channel film by the dielectric layer.

Assignees

Inventors

Classifications

  • Nitride Group III-V materials, e.g. AlN or GaN · CPC title

  • comprising multiple field plate segments · CPC title

  • the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

  • being perpendicular to the channel plane · CPC title

  • H10D64/513Primary

    within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

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Frequently asked questions

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What does patent US9070705B2 cover?
A HEMT semiconductor device can include a dielectric layer that includes a silicon nitride film and an AlN film. In an embodiment, the HEMT semiconductor device can include a GaN film and an AlGaN film. In a process of forming the HEMT device, the AlN can provide an etch stop when forming an opening for a gate electrode.
Who is the assignee on this patent?
Semiconductor Components Ind
What technology area does this patent fall under?
Primary CPC classification H10D64/513. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 30 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).