Semiconductor device

Patent metadata

Field	Value
Publication number	US-9515192-B2
Application number	US-201514848492-A
Country	US
Kind code	B2
Filing date	Sep 9, 2015
Priority date	Jul 31, 2009
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a substrate;
a gate electrode over the substrate;
a first inorganic insulating layer over the gate electrode and the substrate;
a first oxide insulating layer over the first inorganic insulating layer;
an oxide semiconductor layer on and in direct contact with the first oxide insulating layer;
a second oxide insulating layer on and in direct contact with a channel formation region of the oxide semiconductor layer and overlapping with the gate electrode;
a source electrode layer and a drain electrode layer on and in direct contact with a first region and a second region of the oxide semiconductor layer, respectively,
a second inorganic insulating layer over the second oxide insulating layer, on and in direct contact with side edges of the second oxide insulating layer, and on and in direct contact with a third region and a fourth region of the oxide semiconductor layer, the third region being between the channel formation region and one of the first region and the second region, and the fourth region being between the channel formation region and the other of the first region and the second region;
a third inorganic insulating layer over the second inorganic insulating layer;
an organic insulating layer over the third inorganic insulating layer; and
a pixel electrode layer over the organic insulating layer and on and in electrical contact with one of the source electrode layer and the drain electrode layer.

2. The semiconductor device according to claim 1 , wherein each of the first to the third inorganic insulating layers and each of the first and the second oxide insulating layers comprises silicon and at least one of oxygen and nitrogen.

3. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer is in a pixel portion.

4. The semiconductor device according to claim 1 , wherein the second and the third inorganic insulating layers are over the source electrode layer and the drain electrode layer.

5. The semiconductor device according to claim 1 , wherein the second inorganic insulating layer further comprises oxygen.

6. The semiconductor device according to claim 1 , wherein the source electrode layer and the drain electrode layer comprise copper.

7. The semiconductor device according to claim 1 , further comprising a flexible printed circuit affixed to the substrate.

8. A semiconductor device comprising:
a substrate;
a gate electrode over the substrate;
a first inorganic insulating layer over the gate electrode and the substrate;
a first oxide insulating layer over the first inorganic insulating layer;
an oxide semiconductor layer on and in direct contact with the first oxide insulating layer;
a second oxide insulating layer on and in direct contact with a channel formation region of the oxide semiconductor layer and overlapping with the gate electrode;
a source electrode layer and a drain electrode layer on and in direct contact with a first region and a second region of the oxide semiconductor layer, respectively,
a second inorganic insulating layer over the second oxide insulating layer, on and in direct contact with side edges of the second oxide insulating layer, and on and in direct contact with a third region and a fourth region of the oxide semiconductor layer, the third region being between the channel formation region and one of the first region and the second region, and the fourth region being between the channel formation region and the other of the first region and the second region;
a third inorganic insulating layer over the second inorganic insulating layer;
an organic insulating layer over the third inorganic insulating layer; and
a pixel electrode layer over the organic insulating layer and on and in electrical contact with one of the source electrode layer and the drain electrode layer,
wherein the first inorganic insulating layer comprises silicon and nitrogen,
wherein the first oxide insulating layer comprises silicon and oxygen,
wherein the second oxide insulating layer comprises silicon, oxygen, and nitrogen,
wherein the second inorganic insulating layer comprises silicon and nitrogen, and
wherein the third inorganic insulating layer comprises silicon, nitrogen, and oxygen.

9. The semiconductor device according to claim 8 , wherein the oxide semiconductor layer is in a pixel portion.

10. The semiconductor device according to claim 8 , wherein the second and the third inorganic insulating layers are over the source electrode layer and the drain electrode layer.

11. The semiconductor device according to claim 8 , wherein the second inorganic insulating layer further comprises oxygen.

12. The semiconductor device according to claim 8 , wherein the source electrode layer and the drain electrode layer comprise copper.

13. The semiconductor device according to claim 8 , further comprising a flexible printed circuit affixed to the substrate.

14. A semiconductor device comprising:
a substrate;
a first gate electrode over the substrate;
a first inorganic insulating layer over the first gate electrode and the substrate;
a first oxide insulating layer over the first inorganic insulating layer;
an oxide semiconductor layer on and in direct contact with the first oxide insulating layer;
a second oxide insulating layer on and in direct contact with a channel formation region of the oxide semiconductor layer and overlapping with the first gate electrode;
a source electrode layer and a drain electrode layer on and in direct contact with a first region and a second region of the oxide semiconductor layer, respectively,
a second inorganic insulating layer over the second oxide insulating layer, on and in direct contact with side edges of the second oxide insulating layer, and on and in direct contact with a third region and a fourth region of the oxide semiconductor layer, the third region being between the channel formation region and one of the first region and the second region, and the fourth region being between the channel formation region and the other of the first region and the second region;
a third inorganic insulating layer over the second inorganic insulating layer;
an organic insulating layer over the third inorganic insulating layer;
a second gate electrode over the oxide semiconductor layer and overlapping with the first gate electrode; and
a pixel electrode layer over the organic insulating layer and on and in electrical contact with one of the source electrode layer and the drain electrode layer,
wherein the first inorganic insulating layer comprises silicon and nitrogen and is in direct contact with the first gate electrode,
wherein the first oxide insulating layer comprises silicon and oxygen and is in direct contact with the first inorganic insulating layer,
wherein the second oxide insulating layer comprises silicon, oxygen, and nitrogen,
wherein the second inorganic insulating layer comprises silicon and nitrogen, and
wherein the third inorganic insulating layer comprises silicon, nitrogen, and oxygen and is in direct contact with the second inorganic insulating layer.

15. The semiconductor device according to claim 14 , wherein the second gate electrode is over the organic insulating layer.

16. The semiconductor device according to claim 14 , wherein the oxide semiconductor layer is in a drive circuit.

17. The semiconductor device according to claim 14 , wherein the second and the third inorganic insulating layers are over the source electrode layer and the drain electrode layer.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Hosoba Miyuki
• Sakata Junichiro
• Kuwabara Hideaki

Classifications

• G02F1/134336

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• G02F1/1345

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• G09G2300/0426

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• G09G2310/0286

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• G02F1/1339

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