Semiconductor device

Patent metadata

Field	Value
Publication number	US-9236385-B2
Application number	US-201414336142-A
Country	US
Kind code	B2
Filing date	Jul 21, 2014
Priority date	Oct 21, 2009
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.

First claim

The invention claimed is:

1. A memory device comprising:
a memory element comprising a transistor,
the transistor comprising:
a crystalline oxide semiconductor layer including a channel formation region and comprising oxygen, indium, zinc and a metal other than indium and zinc; and
a gate electrode layer over the channel formation region with an insulating film interposed therebetween,

wherein a hydrogen concentration in the crystalline oxide semiconductor layer is less than or equal to 5×10 19 cm −3 , and
wherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than or equal to 1×10 −17 A/μm.

2. The memory device according to claim 1 , wherein a carrier concentration in the crystalline oxide semiconductor layer is less than or equal to 5×10 14 cm −3 .

3. The memory device according to claim 1 , wherein a degree of crystallization of the crystalline oxide semiconductor layer is more than or equal to 80%.

4. The memory device according to claim 1 , wherein a width of the gate electrode layer is larger than a width of the crystalline oxide semiconductor layer in a channel width direction.

5. The memory device according to claim 1 , further comprising:
a first line;
a second line; and
a capacitor,
wherein one of a source and a drain of the transistor is electrically connected to the first line,
wherein the other of the source and the drain of the transistor is electrically connected to one terminal of the capacitor,
wherein the other terminal of the capacitor is electrically connected to the second line.

6. The memory device according to claim 1 , wherein the memory device is a DRAM.

7. A processor comprising:
a timing control circuit;
an instruction decoder operationally connected to the timing control circuit;
a register array;
an address logic and buffer circuit operationally connected to the register array;
a data bus interface operationally connected to the register array;
an arithmetic logic unit operationally connected to the register array; and
an instruction register operationally connected to the instruction decoder and the register array,
wherein at least one of the register array and the instruction register comprises the memory device according to claim 1 .

8. The processor according to claim 7 , wherein the processor is a CPU.

9. A memory device comprising:
a memory element comprising a transistor,
the transistor comprising:
a crystalline oxide semiconductor layer including a channel formation region and comprising oxygen, indium, zinc and a metal other than indium and zinc;
source and drain electrode layers over the crystalline oxide semiconductor layer;
an insulating film over the source and drain electrode layers and in contact with the crystalline oxide semiconductor layer; and
a gate electrode layer over the channel formation region with the insulating film interposed therebetween,

wherein a hydrogen concentration in the crystalline oxide semiconductor layer is less than or equal to 5×10 19 cm −3 , and
wherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than or equal to 1×10 −17 A/μm.

10. The memory device according to claim 9 , wherein a carrier concentration in the crystalline oxide semiconductor layer is less than or equal to 5×10 14 cm −3 .

11. The memory device according to claim 9 , wherein a degree of crystallization of the crystalline oxide semiconductor layer is more than or equal to 80%.

12. The memory device according to claim 9 , wherein a width of the gate electrode layer is larger than a width of the crystalline oxide semiconductor layer in a channel width direction.

13. The memory device according to claim 9 , wherein the memory device is a DRAM.

14. A processor comprising:
a timing control circuit;
an instruction decoder operationally connected to the timing control circuit;
a register array;
an address logic and buffer circuit operationally connected to the register array;
a data bus interface operationally connected to the register array;
an arithmetic logic unit operationally connected to the register array; and
an instruction register operationally connected to the instruction decoder and the register array,
wherein at least one of the register array and the instruction register comprises the memory device according to claim 9 .

15. A memory device comprising:
a memory element comprising a transistor,
the transistor comprising:
a first gate electrode layer;
a crystalline oxide semiconductor layer over the first gate electrode layer with a first insulating film interposed therebetween, the crystalline oxide semiconductor layer including a channel formation region and comprising oxygen, indium, zinc and a metal other than indium and zinc; and
a second gate electrode layer over the channel formation region with a second insulating film interposed therebetween,

wherein the first gate electrode layer and the second gate electrode layer overlap each other with the channel formation region provided therebetween,
wherein a hydrogen concentration in the crystalline oxide semiconductor layer is less than or equal to 5×10 19 cm −3 , and
wherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than or equal to 1×10 −17 A/μm.

16. The memory device according to claim 15 , wherein a carrier concentration in the crystalline oxide semiconductor layer is less than or equal to 5×10 14 cm −3 .

17. The memory device according to claim 15 , wherein a degree of crystallization of the crystalline oxide semiconductor layer is more than or equal to 80%.

18. The memory device according to claim 15 , further comprising:
a first line;
a second line; and
a capacitor,
wherein one of a source and a drain of the transistor is electrically connected to the first line,
wherein the other of the source and the drain of the transistor is electrically connected to one terminal of the capacitor,
wherein the other terminal of the capacitor is electrically connected to the second line.

19. The memory device according to claim 15 , wherein the memory device is a DRAM.

20. A processor comprising:
a timing control circuit;
an instruction decoder operationally connected to the timing control circuit;
a register array;
an address logic and buffer circuit operationally connected to the register array;
a data bus interface operationally connected to the register array;
an arithmetic logic unit operationally connected to the register array; and
an instruction register operationally connected to the instruction decoder and the register array,
wherein at least one of the register array and the instruction register comprises the memory device according to claim 15 .

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Tsubuku Masashi
• Noda Kosei
• Toyotaka Kouhei
• Watanabe Kazunori
• Harada Hikaru

Classifications

• G06F15/76

  Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D62/10

  Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D1/692

  Electrodes · CPC title