Magnetism-controllable dummy structures in memory device

Patent metadata

Field	Value
Publication number	US-9698200-B2
Application number	US-201615287771-A
Country	US
Kind code	B2
Filing date	Oct 7, 2016
Priority date	Oct 8, 2015
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A device and a method of forming a device are disclosed. The method includes providing a substrate defined with first and second functional regions and first and second non-functional regions. The first non-functional region corresponds to a proximate memory region which is proximate to and surrounds the first functional region and the second non-functional region corresponds to an external logic circuit region which surrounds at least the second functional region. A magnetic memory element is formed in the first functional region and a logic element is formed in the second functional region. A plurality of magnetism controllable dummy structures are formed in the proximate memory region and external logic circuit region. The magnetism controllable dummy structures provide uniform magnetic field to the magnetic memory element and prevents electrical-magnetic interaction between the magnetic memory and logic elements on the same substrate.

First claim

What is claimed is:

1. A method of forming a device comprising:
providing a substrate defined with first and second functional regions and first and second non-functional regions, wherein the first non-functional region corresponds to a proximate memory region which is proximate to and surrounds the first functional region and the second non-functional region corresponds to an external logic circuit region which surrounds at least the second functional region;
forming a magnetic memory element in the first functional region and a logic element in the second functional region; and
forming a plurality of magnetism controllable dummy structures in the proximate memory region and external logic circuit region, wherein the magnetism controllable dummy structures provide uniform magnetic field to the magnetic memory element and prevents electrical-magnetic interaction between the magnetic memory and logic elements on the same substrate.

2. The method of claim 1 wherein forming the magnetic memory element comprises forming a magnetic tunnel junction (MTJ) element which comprises a first electrode, a second electrode, and a MTJ stack between the first and second electrodes.

3. The method of claim 2 wherein the MTJ stack comprises at least a magnetically free layer, a magnetically fixed layer, and a tunneling barrier layer between the free and fixed layers.

4. The method of claim 2 wherein forming the magnetism controllable dummy structures comprise forming first type dummy structures in the proximate memory region and forming second type dummy structures in the external logic circuit region.

5. The method of claim 4 wherein the first type dummy structures comprise magnetic dummy structures and the second type dummy structures comprise non-magnetic dummy structures.

6. The method of claim 5 wherein the first type dummy structures comprise a dummy fill structure which is the same as the MTJ element of the magnetic memory element.

7. The method of claim 5 wherein the second type dummy structures comprise a dummy fill structure which is similar as the MTJ element of the magnetic memory element.

8. The method of claim 7 wherein the second type dummy structures comprise a first electrode and a second electrode without a MTJ stack in between the first and second electrodes.

9. A method of forming a device comprising:
providing a substrate defined with first and second functional regions and first and second non-functional regions, wherein the first non-functional region corresponds to a proximate memory region which is proximate to and surrounds the first functional region and the second non-functional region corresponds to an external logic circuit region which surrounds at least the second functional region;
providing a first upper dielectric layer over the first and second functional and non-functional regions of the substrate, wherein the first upper dielectric layer comprises a first upper interconnect level with a plurality of metal lines in the first and second functional and non-functional regions;
forming a magnetic memory element over the first upper dielectric layer in the first functional region and a logic element over the first upper dielectric layer in the second functional region; and
forming a plurality of magnetism controllable dummy structures over the first upper dielectric layer in the first and second non-functional regions, wherein the magnetism controllable dummy structures provide uniform magnetic field to the magnetic memory element and prevents electrical-magnetic interaction between the magnetic memory and logic elements on the same substrate.

10. The method of claim 9 wherein:
forming the magnetic memory element comprises forming a magnetic tunnel junction (MTJ) element sandwiched between top and bottom electrodes over the first upper dielectric layer, wherein the bottom electrode is in direct contact with the metal line in the first upper interconnect level of the first functional region; and
providing a dielectric layer over at least the first and second functional regions and covering the first upper dielectric layer, wherein the dielectric layer comprises a second upper interconnect level with a dual damascene interconnect in the second functional region and a damascene interconnect in the first functional region, wherein the dual damascene interconnect in the second functional region is formed over and is coupled to the metal line in the second functional region and the damascene interconnect in the first functional region is coupled to the MTJ element.

11. The method of claim 10 wherein forming the magnetism controllable dummy structures comprise forming first type dummy structures in the proximate memory region and forming second type dummy structures in the external logic circuit region.

12. The method of claim 11 wherein the first type dummy structures comprise a dummy fill structure which is the same as the MTJ element of the magnetic memory element and the second type dummy structures comprise a dummy fill structure which is similar as the MTJ element of the magnetic memory element.

13. The method of claim 12 wherein the magnetic memory element in the first functional region, the first type dummy structures in the proximate memory region and the second type dummy structures in the external logic circuit region are concurrently formed in the same substrate.

14. The method of claim 12 wherein providing the dielectric layer comprises:
forming a second upper dielectric layer over the first and second functional regions, proximate memory region and external logic circuit region covering the first upper dielectric layer;
patterning the second upper dielectric layer to simultaneously form trench openings at least in the proximate memory region and external logic circuit region, wherein the trench openings extend from a top surface of the second upper dielectric layer to a top surface of the metal line in the proximate memory region and external logic circuit region which accommodate the bottom electrode;
forming a bottom electrode layer over the second upper dielectric layer and fills the trench openings; and
performing a planarization process to remove excess bottom electrode layer to define the bottom electrodes in the proximate memory region and external logic circuit region.

15. The method of claim 14 comprising:
forming various layers of the MTJ stack at least over the proximate memory region and external logic circuit region;
forming a top electrode layer and a hard mask layer over the various layers of the MTJ stack; and
patterning the top electrode layer and various layers of the MTJ stack which comprises
providing a mask over the top electrode layer, and
performing an etch process to remove exposed portions of the top electrode layer and MTJ stack not protected by the mask in the proximate memory region and completely removes the top electrode and various layers of the MTJ stack from the external logic circuit region.

16. The method of claim 15 comprising:
forming an additional upper dielectric layer over at least the first and second functional region, proximate memory region and external logic circuit region;
patterning the additional upper dielectric layer to form trench openings in the proximate memory region and external logic circuit region;
forming an additional top electrode layer over the proximate memory region and external logic circuit region, wherein the additional top electrode layer fills the trench openings in the additional upper dielectric layer; and
performing a planarization process to remove excess additional top elec

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Li Pinghui
• Zhu Ming
• Gong Shunqiang
• Yi Wanbing
• Chan Darin
• Nga Yiang Aun

Classifications

• H01L43/02

  Electricity · mapped topic

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L27/228 Primary

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic