CPU package substrates with removable memory mechanical interfaces

Patent metadata

Field	Value
Publication number	US-9832876-B2
Application number	US-201414575775-A
Country	US
Kind code	B2
Filing date	Dec 18, 2014
Priority date	Dec 18, 2014
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.

First claim

What is claimed is:

1. A package substrate, comprising:
a processing device interface to couple to a processing device;
a memory device electrical interface disposed on the package substrate;
a removable memory mechanical interface disposed proximately to the memory device electrical interface, the removable memory mechanical interface to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate and without removing the processing device.

2. The package substrate of claim 1 , wherein the memory device electrical interface comprises a land grid array.

3. The package substrate of claim 1 , wherein the memory device electrical interface comprises an array of pins.

4. The package substrate of claim 1 , wherein the removable memory mechanical interface has electrical contacts that are in contact with the memory device electrical interface and has exposed electrical contacts for electrical contact to a mechanical counterpart that is to mate with the removable memory mechanical interface and that is integrated with the memory device.

5. The package substrate of claim 1 , wherein the removable memory mechanical interface is a sliding rail socket.

6. The package substrate of claim 5 , wherein the sliding rail socket that comprises an array of angled pins, sliding grooves on two opposing sides of the socket, and a stopping wall.

7. The package substrate of claim 6 , wherein the angled pins are slanted toward the stopping wall.

8. The package substrate of claim 1 , wherein the removable memory mechanical interface is a multi-edge connector socket.

9. The package substrate of claim 8 , wherein the multi-edge connector socket is a double edge socket comprising:
a first portion and a second portion connected at a joint, the first portion extending in a direction at an offset angle from the second portion;
an opening extending through the joint and along both the first and second portions; and
an array of contacts extending in a direction at an angle half of the offset angle from one of the first and second portion.

10. The package substrate of claim 9 , wherein the first and second portions have a beveled corner that extends in a direction parallel to the array of contacts.

11. The package substrate of claim 8 , wherein the multi-edge connector socket is a full edge pin grid array socket, comprising:
a structure body in the shape of a frame; and

a plurality of openings in a top surface of the structure body.

12. The package substrate of claim 1 , wherein the removable memory mechanical interface comprises a housing structure, an array of openings in the housing structure, and an array of pins.

13. The package substrate of claim 12 , wherein each pin of the array of pins is disposed in each opening in the array of openings.

14. The package substrate of claim 13 , wherein each pin has a curved contacting end.

15. The package substrate of claim 14 , wherein a first distance from the tip of the curved contacting end to the equator of the curved contacting end is less than a second distance from the tip of an interconnecting solder ball to the equator of the interconnecting solder ball.

16. The package substrate of claim 12 , wherein each opening of the array of openings comprises an interconnection region and a pin deflection region of the solder ball region, the pin deflection region extending from the solder ball region.

17. The package substrate of claim 1 , wherein the removable memory mechanical interface is coupled to a counterpart comprised of a strip of flex cable having two opposing ends and a memory device located at one of the opposing ends.

18. The package substrate of claim 17 , wherein the flex cable has a connection portion at one of the opposing ends, the connection portion mated with the memory device electrical interface.

19. The package substrate of claim 17 , wherein the flex cable has a second memory device at the other of the opposing ends and a connection portion between the memory devices, the connection portion mated with the memory device electrical interface.

20. The package substrate of claim 17 , wherein the memory device is attached to a heat sink of a processing device that is connected to the processing device interface.

21. The package substrate of claim 1 , wherein the removable mechanical interface comprises a pair of sockets with openings disposed horizontally within each socket of the pair of sockets, the memory device to fit horizontally between the pair of sockets.

22. The package substrate of claim 21 , wherein the pair of sockets have a height that permits the pair of sockets and the memory device to reside beneath a heat sink of a processing device that is connected to the processing device interface.

23. The package substrate of claim 1 , wherein the removable memory mechanical interface is a frame socket that comprises an alignment frame and a land grid array, the alignment frame having a notch within one side.

24. The package of claim 1 , wherein the frame socket is to support reflowable removal of the memory device from the package substrate.

25. The package substrate of claim 1 , wherein the removable memory mechanical interface includes a set of alignment holes.

26. The package substrate of claim 1 , wherein the removable memory mechanical interface includes a set of alignment pins.

27. The package substrate of claim 1 , wherein the removable memory mechanical interface is a spring-loaded clip.

28. A package system, comprising:
a package substrate;
a processing device coupled to the package substrate;
a memory device electrical interface disposed on the package substrate;
a removable memory mechanical interface disposed proximate to the memory device electrical interface; and
a memory device attached to the memory device electrical interface by the removable memory mechanical interface, the removable memory device mechanical interface to permit the memory device to be easily detachable and re-attachable to the memory device electrical interface without removing the processing device.

29. The package system of claim 28 , further comprising a reflowable grid array disposed between the memory device electrical interface and the memory device.

30. The package system of claim 28 , wherein the memory device is electrically coupled to the processing device on the package substrate.

31. A method of fabricating a package system, comprising:
attaching a processing device to a package substrate; and
attaching a memory device to the package substrate by attaching a memory device substrate to a removable memory mechanical interface disposed on the package substrate around a memory device electrical interface; and,
removing the memory device from the package substrate without removing the processing device.

32. The method of claim 31 , wherein the memory device substrate is attached by inserting the memory device substrate into a socket of the removable memory mechanical interface.

33. The method of claim 31 , wherein the memory device is attached by sliding the memory device substrate into sliding grooves of the removable memory mechanical interface.

34. The method of claim 31 , wherein the memory device is attached by press

Assignees

• Intel Corp

Inventors

• Prakash Mani
• Holden Thomas T
• Smalley Jeffory L
• Viswanath Ram S
• Coury Bassam N
• Ziakas Dimitrios
• Zhao Chong J
• Thibado Jonathan W
• Murtagian Gregorio R
• Liu Kuang C
• Swaminathan Rajasekaran
• Zhang Zhichao
• Lynch John M
• Llapitan David J
• Ganesan Sanka
• Li Xiang
• Vergis George

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W70/60 Primary

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title