Stacked memory chip solution with reduced package inputs/outputs (i/os)
US-2025349327-A1 · Nov 13, 2025 · US
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Zhao Chong J patents
Zhao Chong J is listed as an inventor on 24 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Zhao Chong J |
| Total patents | 24 |
| First publication | Jul 13, 2017 |
| Latest publication | Nov 13, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Stacked memory chip solution with reduced package inputs/outputs (I/Os)
US-12340863-B2 · Jun 24, 2025 · US
Techniques to couple high bandwidth memory device on silicon substrate and package substrate
US-2025006250-A1 · Jan 2, 2025 · US
Enhanced i/o semiconductor chip package and cooling assembly having side i/os
US-2024421025-A1 · Dec 19, 2024 · US
Techniques to couple high bandwidth memory device on silicon substrate and package substrate
US-12087352-B2 · Sep 10, 2024 · US
Package pin pattern for device-to-device connection
US-12073906-B2 · Aug 27, 2024 · US
Techniques to couple high bandwidth memory device on silicon substrate and package substrate
US-2024029785-A1 · Jan 25, 2024 · US
Techniques to couple high bandwidth memory device on silicon substrate and package substrate
US-11776619-B2 · Oct 3, 2023 · US
Techniques to couple high bandwidth memory device on silicon substrate and package substrate
US-2023145937-A1 · May 11, 2023 · US
Techniques to couple high bandwidth memory device on silicon substrate and package substrate
US-11557333-B2 · Jan 17, 2023 · US
Recent patents
Latest publications not already listed above.
Techniques to couple high bandwidth memory device on silicon substrate and package substrate
US-2021335414-A1 · Oct 28, 2021 · US
Stacked memory chip solution with reduced package inputs/outputs (i/os)
US-2021335393-A1 · Oct 28, 2021 · US
Techniques to couple high bandwidth memory device on silicon substrate and package substrate
US-11056179-B2 · Jul 6, 2021 · US
Package pin pattern for device-to-device connection
US-2021074333-A1 · Mar 11, 2021 · US
DIMM for a high bandwidth memory channel
US-10884958-B2 · Jan 5, 2021 · US
Techniques to couple high bandwidth memory device on silicon substrate and package substrate
US-2020143870-A1 · May 7, 2020 · US
Techniques to access or operate a dual in-line memory module via multiple data channels
US-10592445-B2 · Mar 17, 2020 · US
Techniques to access or operate a dual in-line memory module via multiple data channels
US-2019213148-A1 · Jul 11, 2019 · US
Dimm for a high bandwidth memory channel
US-2019042500-A1 · Feb 7, 2019 · US
Back-end memory channel that resides between first and second dimm slots and applications thereof
US-2019042162-A1 · Feb 7, 2019 · US
Techniques to access or operate a dual in-line memory module via multiple data channels
US-10146711-B2 · Dec 4, 2018 · US
Cpu package substrates with removable memory mechanical interfaces
US-2018007791-A1 · Jan 4, 2018 · US
CPU package substrates with removable memory mechanical interfaces
US-9832876-B2 · Nov 28, 2017 · US
Techniques to Access or Operate a Dual In-Line Memory Module via Multiple Data Channels
US-2017199830-A1 · Jul 13, 2017 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 18 |
| Tahoe Res Ltd | 6 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C5/04 | 16 |
| G11C11/4096 | 13 |
| G11C7/1045 | 13 |
| G11C7/10 | 13 |
| H10W90/00 | 12 |