Automatic buffer sizing for optimal network-on-chip design

Patent metadata

Field	Value
Publication number	US-9825887-B2
Application number	US-201715438684-A
Country	US
Kind code	B2
Filing date	Feb 21, 2017
Priority date	Feb 3, 2015
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

The present disclosure relates to automatic sizing of NoC channel buffers of one or more virtual channels to optimize NoC design, SoC design, and to meet defined performance objectives. The present disclosure further relates to a NoC element such as a router or a bridge having input ports associated with input virtual channels, and output ports associated with output virtual channels, wherein, aspects of the present disclosure enable sizing of any or a combination of the width of the input virtual channel(s), width of the output virtual channel(s), buffer(s) associated with input virtual channels, and buffer(s) associated with output virtual channels. In another aspect, the sizing can be performed based on one or a combination of defined performance objectives, throughputs of the input virtual channels, and throughputs of the output virtual channels, load characteristics, bandwidth characteristics of each input/output channel, among other like parameters.

First claim

What is claimed is:

1. A method for generating a Network on Chip (NoC), comprising:
generating the NoC comprising a hardware element comprising an input channel and an an output channel, the generating the NoC comprising:
sizing the input channel and the output channel of the NoC based on flow control of the hardware element;
adjusting a buffer size of a buffer associated with the input channel based on a performance objective and a throughput of at least one of the input channel and output channel; and
adjusting a buffer size of a buffer associated with the output channel based on the performance objective and the throughput of the at least one of the output channel and input channel.

2. The method of claim 1 , wherein the flow control of the input channel and the output channel is derived from one or more of: clock frequency, read frequency, and write frequency.

3. The method of claim 1 , wherein the performance objective is based on at least one of: rate of traffic, message size distribution of the traffic, channel width, channel clock frequency, arbitration efficiency of the router, traffic burstiness, and specified overprovisioning.

4. The method of claim 1 , wherein the adjusting the buffer size comprises adjusting the buffer size based on the performance objective, and input/output message sizes and input/output message rate.

5. The method of claim 1 , wherein the adjusting the buffer size is based on a flow control turnaround time between a transmitting hardware element and a receiving hardware element.

6. The method of claim 1 , wherein the adjusting the buffer size is based on a clock frequency of a transmitting hardware element and a receiving hardware element.

7. A non-transitory computer readable medium storing instructions for executing a process for generating a Network on Chip (NoC), the instructions comprising:
generating the NoC comprising a hardware element comprising an input channel and an a output channel, the generating the NoC comprising:
sizing each of the input channel and the output channel of the NoC based on flow control of the hardware element;
adjusting a buffer size of a buffer associated with the input channel based on a performance objective and a throughput of at least one of the input channel and output channel; and
adjusting a buffer size of a buffer associated with the output channel based on the performance objective and the throughput of the at least one of the output channel and input channel.

8. The non-transitory computer readable medium of claim 7 , wherein the flow control of the input channel and the output channel is derived from one or more of: clock frequency, read frequency, and write frequency.

9. The non-transitory computer readable medium of claim 7 , wherein the performance objective is based on at least one of: rate of traffic, message size distribution of the traffic, channel width, channel clock frequency, arbitration efficiency of the router, traffic burstiness, and specified overprovisioning.

10. The non-transitory computer readable medium of claim 7 , wherein the adjusting the buffer size comprises adjusting the buffer size based on the performance objective, and input/output message sizes and input/output message rate.

11. The non-transitory computer readable medium of claim 7 , wherein the adjusting the buffer size is based on a flow control turnaround time between a transmitting hardware element and a receiving hardware element.

12. The non-transitory computer readable medium of claim 7 , wherein the adjusting the buffer size is based on a clock frequency of a transmitting hardware element and a receiving hardware element.

13. A system configured to generate a Network on Chip (NoC), comprising:
a processor configured to generate a NoC comprising a hardware element comprising an input channel and an output channel, the processor configured to:
size each of the input channel and the output channel of the NoC based on flow control of the hardware element;
adjust a buffer size of a buffer associated with the input channel based on a performance objective and a throughput of at least one of the input channel and output channel; and
adjust a buffer size of a buffer associated with the output channel based on the performance objective and the throughput of the at least one of the output channel and input channel.

14. The system of claim 13 , wherein the flow control of the input channel and the output channel is derived from one or more of: clock frequency, read frequency, and write frequency.

15. The system of claim 13 , wherein the performance objective is based on at least one of:
rate of traffic, message size distribution of the traffic, channel width, channel clock frequency, arbitration efficiency of the router, traffic burstiness, and specified overprovisioning.

16. The system of claim 13 , wherein adjustment of the buffer size comprises adjustment of the buffer size based on the performance objective, and input/output message sizes and input/output message rate.

17. The system of claim 13 , wherein adjustment of the buffer size is based on a flow control turnaround time between a transmitting hardware element and a receiving hardware element.

18. The system of claim 13 , wherein adjustment of the buffer size is based on a clock frequency of a transmitting hardware element and a receiving hardware element.

Assignees

• Netspeed Systems Inc
• Netspeed Systems

Inventors

• Kumar Sailesh

Classifications

• H04L41/12

  Discovery or management of network topologies · CPC title

• H04L49/109

  Integrated on microchip, e.g. switch-on-chip · CPC title

• H04L49/9005 Primary

  using dynamic buffer space allocation · CPC title

• H04L43/0894

  Packet rate · CPC title

• H04L47/283

  in response to processing delays, e.g. caused by jitter or round trip time [RTT] · CPC title