Hierarchical asymmetric mesh with virtual routers

Patent metadata

Field	Value
Publication number	US-9253085-B2
Application number	US-201213723732-A
Country	US
Kind code	B2
Filing date	Dec 21, 2012
Priority date	Dec 21, 2012
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A network-on-chip configuration includes a first plurality of cores arranged in a two-dimensional mesh; a first plurality of routers, each of the first plurality of routers associated with a corresponding local one of the first plurality of cores, each of the first plurality of routers having a plurality of directional ports configured to provide connections to other ones of the first plurality of routers; a second plurality of cores disposed around a periphery of the two-dimensional mesh arrangement; and a second plurality of routers, each of the second plurality of routers associated with a corresponding local one of the second plurality of cores, and having a directional port configured to provide a connection to a neighboring one of the first plurality of routers.

First claim

What is claimed is:

1. A method, comprising:
for a network on chip (NOC) configuration comprising a plurality of cores interconnected by a plurality of routers in a mesh arrangement, generating a plurality of virtual routers configured to connect ones of the plurality of routers having one or more unused ports; and
configuring each of the plurality of virtual routers to connect to an unused port of a router from the ones of the plurality of routers having the one or more unused ports.

2. The method of claim 1 , wherein a host is connected to one of the plurality of virtual routers connected to a previously unused port of one of the plurality of routers.

3. The method of claim 1 , further comprising configuring each of the plurality of virtual routers with at least one of a register and a flow control logic between a host port and a router port of the each of the plurality of the virtual routers, and a pass through logic facilitating a direct connection between the host port and the router port of the each of the plurality of the virtual routers.

4. The method of claim 1 , further comprising routing a message through the NOC configuration by using multi-turn based routing in the mesh arrangement.

5. The method of claim 4 , further comprising limiting a number of turns for the message and determining a path in the mesh arrangement based on the limiting.

6. A non-transitory computer readable storage medium storing instructions for executing a process, the instructions comprising:
for a network on chip (NOC) configuration comprising a plurality of cores interconnected by a plurality of routers in a mesh arrangement, generating a plurality of virtual routers configured to connect ones of the plurality of routers having one or more unused ports; and
configuring each of the plurality of virtual routers to connect to an unused port of a router from the ones of the plurality of routers having the one or more unused ports.

7. The non-transitory computer readable storage medium of claim 6 , wherein a host is connected to one of the plurality of virtual routers connected to a previously unused port of one of the plurality of routers.

8. The non-transitory computer readable storage medium of claim 6 , wherein the instructions further comprise configuring each of the plurality of virtual routers with at least one of a register and a flow control logic between a host port and a router port of the each of the plurality of the virtual routers, and a pass through logic facilitating a direct connection between the host port and the router port of the each of the plurality of the virtual routers.

9. The non-transitory computer readable storage medium of claim 6 , wherein the instructions further comprise routing a message through the NOC configuration by using multi-tum based routing in the mesh arrangement.

10. The non-transitory computer readable storage medium of claim 9 , wherein the instructions further comprise limiting a number of turns for the message and determining a path in the mesh arrangement based on the limiting.

11. An apparatus, comprising:
a processor, configured to:
for a network on chip (NOC) configuration comprising a plurality of cores interconnected by a plurality of routers in a mesh arrangement, generate a plurality of virtual routers configured to connect ones of the plurality of routers having one or more unused ports; and
configure each of the plurality of virtual routers to connect to an unused port of a router from the ones of the plurality of routers having the one or more unused ports.

12. The apparatus of claim 11 , wherein a host is connected to one of the plurality of virtual routers connected to a previously unused port of one of the plurality of routers.

13. The apparatus of claim 11 , wherein the processor is configured to configure each of the plurality of virtual routers with at least one of a register and a flow control logic between a host port and a router port of the each of the plurality of the virtual routers, and a pass through logic facilitating a direct connection between the host port and the router port of the each of the plurality of the virtual routers.

14. The apparatus of claim 11 , wherein the processor is configured to route a message through the NOC configuration by using multi-turn based routing in the mesh arrangement.

15. The apparatus of claim 14 , wherein the processor is configured to limit a number of turns for the message and determining a path in the mesh arrangement based on the limiting.

Assignees

• Kumar Sailesh
• Norige Eric
• Philip Joji
• Hassan Mahmud
• Mitra Sundari
• Rowlands Joseph
• Netspeed Systems

Inventors

• Kumar Sailesh
• Norige Eric
• Philip Joji
• Hassan Mahmud
• Mitra Sundari
• Rowlands Joseph

Classifications

• H04L45/04

  Interdomain routing, e.g. hierarchical routing · CPC title

• H04L45/58 Primary

  Association of routers · CPC title