Integrated NoC for performing data communication and NoC functions

Patent metadata

Field	Value
Publication number	US-9319232-B2
Application number	US-201414245917-A
Country	US
Kind code	B2
Filing date	Apr 4, 2014
Priority date	Apr 4, 2014
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

The present disclosure is directed to a NoC interconnect that consolidates one or more Network on Chip functions into one Network on Chip. The present disclosure is further directed to a Network on Chip (NoC) interconnect comprising a plurality of first agents, wherein each agent can be configured to communicate with other ones of the plurality of first agents. NoC of the present disclosure can further include a second agent configured to perform a NoC function, and a bridge associated with the second agent, wherein the bridge can be configured to packetize messages from the second agent to the plurality of first agents, and to translate messages from the plurality of first agents to the second agent.

First claim

What is claimed is:

1. A Network on Chip (NoC), comprising:
a plurality of first agents, each of the plurality of first agents configured as a NoC host to communicate with other ones of the plurality of first agents through injection of messages into the NoC;
a second agent configured to perform a NoC function; and
a bridge connected to the second agent, the bridge configured to packetize messages from the second agent to transmit to the plurality of first agents, and to translate the messages from the plurality of first agents to the second agent,
wherein the NoC function is a register access and configuration management function that provides read and write access to one or more configuration registers of the plurality of first agents and to one or more interconnects of the plurality of first agents.

2. The NoC of claim 1 , wherein the second NoC agent is associated with an interconnect network comprising at least one separate set of one or more dedicated channels.

3. The NoC of claim 2 , wherein the one or more dedicated channels are isolated from the one or more interconnects of the plurality of first agents, and wherein the one or more dedicated channels are configured to handle traffic between the second agent and the plurality of first agents.

4. The NoC of claim 2 , wherein each of the one or more dedicated channels is one of a virtual channel and a physical channel.

5. A non-transitory computer readable medium storing instructions for executing a process, the instructions comprising:
configuring each of a plurality of first agents as a Network on Chip (NoC) host to communicate with other ones of the plurality of first agents through injection of messages into the NoC;
configuring a second agent to perform a NoC function; and
configuring a bridge connected to the second agent to packetize messages from the second agent to transmit to the plurality of first agents, and to translate the messages from the plurality of first agents to the second agent,
wherein the NoC function is a register access and configuration management function that provides read and write access to one or more configuration registers of the plurality of first agents and to one or more interconnects of the plurality of first agents.

6. The non-transitory computer readable medium of claim 5 , wherein the instructions further comprise associating the second NoC agent with an interconnect network comprising at least one separate set of one or more dedicated channels.

7. The non-transitory computer readable medium of claim 6 , wherein the instructions further comprise isolating the one or more dedicated channels from the one or more interconnects of the plurality of first agents, and configuring the one or more dedicated channels to handle traffic between the second agent and the plurality of first agents.

8. The non-transitory computer readable medium of claim 6 , wherein each of the one or more dedicated channels is one of a virtual channel and a physical channel.

Assignees

• Netspeed Systems

Inventors

• Kumar Sailesh

Classifications

• H04L49/604

  Hybrid IP/Ethernet switches · CPC title

• G06F15/7825

  Globally asynchronous, locally synchronous, e.g. network on chip · CPC title

• H04L12/28 Primary

  characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks] (wireless communication networks H04W {; arrangements for dividing the transmission path H04W40/00}) · CPC title

• H04L49/15 Primary

  Interconnection of switching modules · CPC title

• H04L12/6418

  Hybrid transport · CPC title