Using multiple traffic profiles to design a network on chip

Patent metadata

Field	Value
Publication number	US-9294354-B2
Application number	US-201314062618-A
Country	US
Kind code	B2
Filing date	Oct 24, 2013
Priority date	Oct 24, 2013
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

The present application is directed to designing an efficient Network on Chip (NoC) interconnect architecture that is adaptable to varied interface protocols of different SoC components/hosts and is compliant to handle different types and models of traffic profiles. Aspects of the present application include a method, which may involve utilizing multiple traffic profiles described in a specification to generate a NoC that satisfies all the traffic profiles. Such a NoC interconnect architecture can be formed from multiple traffic profiles by generating a single consolidated traffic profile from individual or subset based dependency graphs of the multiple traffic profiles.

First claim

What is claimed is:

1. A method, comprising:
generating a network on chip (NoC) from a specification, the specification comprising a plurality of traffic profiles and requirement information for each of the plurality of traffic profiles, wherein the NoC is configured to satisfy one or more requirements indicated in the requirement information of the each of the plurality of traffic profiles in the specification;
wherein the requirement information for each of the plurality of traffic profiles comprises at least one of: a bandwidth requirement, a latency requirement, and a Quality of Service (QoS) requirement, protocol and dependency requirements between various messages, clock frequency requirements of System on Chip (SoC) agents, and power domain and power sequence requirements of the SoC agents;
wherein the specification comprises subset information indicative of one or more subsets of the plurality of traffic profiles that can co-exist during a same time window;
wherein the generating the NoC from the specification is performed automatically based on a dependency graph from a deadlock avoidance process and a consolidation of the plurality of traffic profiles from a topology design process.

2. The method of claim 1 , wherein the specification comprises clock frequency information and power domain information for each of the plurality of traffic profiles.

3. The method of claim 1 , wherein the deadlock avoidance process comprises creating the dependency graph from the plurality of traffic profiles and determining dependencies within one or more subsets of the plurality of traffic profiles that can co-exist during a same time window.

4. The method of claim 1 , wherein the topology design process comprises generating a single traffic profile from the plurality of traffic profiles.

5. The method of claim 4 , wherein the topology design process further comprises:
determining a bandwidth requirement for each flow of the single traffic profile based on a sum of bandwidth requirements of flows in a subset of the traffic profiles that co-exist during a same time window; and
performing link sizing, virtual channel allocation, and determination of NoC topology, and routes and number of NoC layers, for the single traffic profile based on the determined bandwidth requirement for the each flow of the traffic profile.

6. The method of claim 4 , wherein the topology design process further comprises:
determining a latency requirement for each flow of the single traffic profile based on a minimum latency requirement of flows in a subset of the traffic profiles that co-exist during a same time window; and
consolidating Quality of Service (QoS) requirements for the each flow for the single traffic profile from the flows.

7. A non-transitory computer readable storage medium storing instructions for executing a process, the instructions comprising:
Generating a network on chip (NoC) from a specification, the specification comprising a plurality of traffic profiles and requirement information for each of the plurality of traffic profiles, wherein the NoC is configured to satisfy one or more requirements indicated in the requirement information of the each of the plurality of traffic profiles in the specification;
wherein the requirement information for each of the plurality of traffic profiles comprises at least on of: a bandwidth requirement, a latency requirement, and a Quality of Service (QoS) requirement, protocol and dependency requirements between various messages, clock frequency requirements of System on Chip (SoC) agents, and power domain and power sequence requirements of the SoC agents;
wherein the specification comprises subset information indicative of one or more subsets of the plurality of traffic profiles that can co-exist during a same time window;
wherein the generating the NoC from the specification is performed automatically based on a dependency graph from a deadlock avoidance process and a consolidation of the plurality of traffic profiles from a topology design process.

8. The non-transitory computer readable storage medium of claim 7 , wherein the specification comprises clock frequency information and power domain information for each of the plurality of traffic profiles.

9. The non-transitory of computer readable storage medium of claim 7 , wherein the deadlock avoidance process comprises creating the dependency graph from the plurality of traffic profiles and determining dependencies within one or more subsets of the plurality of traffic profiles that can co-exist during a same time window.

10. The non-transitory computer readable storage medium of claim 7 , wherein the topology design process comprises generating a single traffic profile from the plurality of traffic profiles.

11. The non-transitory computer readable storage medium of claim 10 , wherein the topology design process further comprises:
determining a bandwidth requirement for each flow of the single traffic profile based on a sum of bandwidth requirements of flows in a subset of the traffic profiles that co-exist during a same time window; and
performing link sizing, virtual channel allocation, and determination of NoC topology, and routes and number of NoC layers, for the single traffic profile based on the determined bandwidth requirement for the each flow of the traffic profile.

12. The non-transitory computer readable storage medium of claim 10 , wherein the topology design process further comprises:
determining a latency requirement for each flow of the single traffic profile based on a minimum latency requirement of flows in a subset of the traffic profiles that co-exist during a same time window; and
consolidating Quality of Service (QoS) requirements for the each channel for the single traffic profile from the plurality of traffic profiles of the each channel.

Assignees

• Netspeed Systems

Inventors

• Kumar Sailesh

Classifications

• H04L41/083 Primary

  for increasing network speed · CPC title

• H04L41/145

  involving simulating, designing, planning or modelling of a network · CPC title

• H04L41/0806

  for initial configuration or provisioning, e.g. plug-and-play · CPC title

• G06F15/7807

  System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title