Extensible time space switch systems and methods

Patent metadata

Field	Value
Publication number	US-9825883-B2
Application number	US-78845310-A
Country	US
Kind code	B2
Filing date	May 27, 2010
Priority date	May 27, 2010
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

The present disclosure provides a structured, pipelined large time-space switch and method of operation resolving interconnect complexity. The time-space switch results in an interconnect complexity that does not grow as the spatial dimension is increased and results in a reduction of long high fan-out nets, a quicker layout, and improved clock speed. With respect to time-space switch fabric implementation, the present invention improves the maximum clock frequency of the switch fabric, and improves integrated circuit layout time by eliminating long high fan-out nets. Certain high-speed large switch fabrics may not be realizable without this implementation, and it significantly reduces implementation time (and cost). The present invention may include link encoding of switch frames by mapping 8B10B control characters into an 64B65B format (similar to Generic Framing Protocol-Transparent (GFP-T)), wrapping 32 65B encoded words with an 11-bit error correcting code, and scrambling the frame with a frame synchronous scrambler.

First claim

What is claimed is:

1. A pipelined time-space switch, comprising:
input circuitry comprising N input links each receiving M timeslots of data, wherein N and M are integers;
a two-dimensional matrix of a plurality of timeslot interchangers, wherein the two-dimensional matrix is configured to receive from the input circuitry each of the M timeslots from the N input links in a pipelined manner where each of the plurality of timeslot interchangers interconnect to adjacent neighbors only;
output circuitry comprising N output links configured to receive any of the M timeslots from any of the N input links from the two-dimensional matrix;
wherein the input circuitry is located orthogonal to the output circuitry and each of the input circuitry and the output circuitry are adjacent to the two-dimensional matrix; and
wherein input data flows from the input circuitry orthogonal to the output circuitry, and wherein output data and control flows to the output circuitry orthogonal to the input circuitry; and
common control circuitry parallel to the input circuitry, wherein the common control circuitry is communicatively coupled to separate configuration memories for each of the N output links parallel to the output circuitry, wherein the configuration memories are configured to control the data flow to the output circuitry for their respective output links, wherein the configuration memories are directly coupled to a first column of the plurality of timeslot interchangers and not directly coupled to other columns of the plurality of timeslot interchangers, wherein addressing from the configuration memories is pipelined through the two-dimensional matrix, and wherein the common control circuitry, for providing launch signals with the addressing to the two-dimensional matrix, is connected to the input circuitry and the configuration memories,
wherein the input circuitry and the output circuitry respectively comprise input framers and output framers which utilize efficient line coding relative to 8B10B, comprising of SLP112 timeslot data framing, 64B65B encoding, Fire code forward error correction, and scrambling.

2. The pipelined time-space switch of claim 1 , wherein the pipelined manner provides interconnect complexity that does not grow as spatial dimension is increased and results in a reduction of long high fan-out nets.

3. The pipelined time-space switch of claim 1 , wherein the input circuitry comprises input framers for each of the N input links; and wherein the output circuitry comprises output framers for each of the N output links.

4. The pipelined time-space switch of claim 1 , wherein each of the plurality of timeslot interchangers comprises of 8×8 link cascadable time-space switches.

5. The pipelined time-space switch of claim 1 , wherein the pipelined time-space switch is configurable as one of an ingress switch, a center stage switch, and an egress switch.

6. A pipelined time-space switch, comprising:
input circuitry comprising N input links each receiving M timeslots, wherein N and M are integers;
a two-dimensional matrix of a plurality of time-space switches, wherein the two-dimensional matrix is configured to receive from the input circuitry each of the M timeslots from the N input links in a pipelined manner where each of the plurality of time-space switches interconnect to adjacent neighbors only; and
output circuitry comprising N output links configured to receive any of the M timeslots from any of the N links from the two-dimensional matrix;
wherein the input circuitry is located orthogonal to the output circuitry and each of the input circuitry and the output circuitry are adjacent to the two-dimensional matrix; and
wherein input data flows from the input circuitry orthogonal to the output circuitry, and wherein output data and control flows to the output circuitry orthogonal to the input circuitry; and
common control circuitry parallel to the input circuitry, wherein the common control circuitry is communicatively coupled to separate configuration memories for each of the N output links parallel to the output circuitry, wherein the configuration memories are configured to control the data flow to the output circuitry for their respective links, wherein the configuration memories are directly coupled to a first column of the plurality of time-space switches and not directly coupled to other columns of the plurality of time-space switches, wherein addressing from the configuration memories is pipelined through the two-dimensional matrix, and wherein the common control circuitry, for providing launch signals with the addressing to the two-dimensional matrix, is connected to the input circuitry and the configuration memories,
wherein the input circuitry comprises input framers for each of the N input links; wherein the output circuitry comprises output framers for each of the N output links; and wherein the input framers and the output framers utilize efficient line coding relative to 8B10B, comprising of SLP112 timeslot data framing, 64B65B encoding, Fire code forward error correction and scrambling.

7. The pipelined time-space switch of claim 6 , wherein the pipelined manner provides interconnect complexity that does not grow as spatial dimension is increased and results in a reduction of long high fan-out nets.

8. The pipelined time-space switch of claim 7 , wherein each of the plurality of time-space switches comprises a memory tile configured to operate as an 8×8 time-space switch.

9. The pipelined time-space switch of claim 8 , wherein the pipelined time-space switch comprises N 2 of the memory tiles interconnected in the pipelined manner thereby providing an overall 8N×8N link time-space switch, where N is an integer.

10. The pipelined time-space switch of claim 6 , wherein the pipelined time-space switch is configurable as one of an ingress switch, a center stage switch, and an egress switch.

11. A pipelined time-space switching method, comprising:
receiving M timeslots over each of N input links, N and M are integers;
loading each of the M timeslots for each of the N input links in a two-dimensional matrix in a pipelined fashion where interconnections in the two-dimensional matrix are only between adjacent neighbors only;
reading out any of the M timeslots from any of the N output links from the two-dimensional matrix;
wherein input circuitry receiving the M timeslots is located orthogonal to output circuitry reading out the any of the M timeslots and each of the input circuitry and the output circuitry are adjacent to the two-dimensional matrix; and
providing common control circuitry parallel to the input circuitry, wherein the common control circuitry is communicatively coupled to separate configuration memories for each of the N output links parallel to the output circuitry, wherein the configuration memories are configured to control the data flow to the output circuitry for their respective links, wherein the configuration memories are directly coupled to a first column of the two-dimensional matrix and not directly coupled to other columns of the two-dimensional matrix, wherein addressing from the configuration memories is pipelined through the two-dimensional matrix, and wherein the common control circuitry, is connected to the input circuitry and the configuration memories,
wherein the input circuitry and the output circuitry respectively comprise input framers and output framers which utilize efficient line coding relative to 8B10B, comprising of SLP112 timeslot data framing, 64B65B encoding, Fire code forward error correction, and scrambling.

12. The pipelined time-space switching method of claim 11 , wherein the pipelined fashion provides int

Assignees

• Nichols Jeffery Thomas
• Dublin Ian
• Bengough Peter
• Sabourin Andre
• Ciena Corp

Inventors

• Nichols Jeffery Thomas
• Dublin Ian
• Bengough Peter
• Sabourin Andre

Classifications

• H04L49/00

  Packet switching elements · CPC title

• H04Q2213/13393

  Time slot switching, T-stage, time slot interchanging, TSI · CPC title

• H04L49/45

  Arrangements for providing or supporting expansion · CPC title

• H04L49/103 Primary

  using a shared central buffer; using a shared memory · CPC title