Packet memory system, method and device for preventing underrun

Patent metadata

Field	Value
Publication number	US-2016294729-A1
Application number	US-201514673807-A
Country	US
Kind code	A1
Filing date	Mar 30, 2015
Priority date	Mar 30, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

A packet memory system for selectively outputting received packets on one or more output ports. The packet memory system including a controller for controlling the output ports. Specifically, for packets of multicast or broadcast traffic that needs to be output from a plurality of the ports, the controller designates one or more reader ports that read the packet data from a packet memory such that the remainder of the ports are able to simply listen for the read packet data without performing a read operation.

First claim

We claim:

1 . A packet memory system, the system comprising:
a non-transitory computer-readable packet memory comprising one or more memory banks for storing packet data of a packet input by the system, wherein the packet data as stored on the memory banks is organized according to one or more pages mapped to the memory banks; a plurality of output ports coupled with the packet memory and configured to selectively read the packet data from the packet memory and output the packet data out of the system; and a controller coupled with the plurality of output ports for controlling which of the ports output the packet data, wherein if the packet data is to be output from two or more of the ports, the controller commands less than all of the two or more of the ports to cause the packet data to be read out from the packet memory and transmitted to all of the two or more of the ports.

2 . The system of claim 1 , wherein the plurality of output ports and the controller are operating in a cut-thru mode such that each of the plurality of output ports begin to output packet data before the entirety of the packet has been received.

3 . The system of claim 2 , wherein the controller commands all of the two or more of the ports to listen for and output the packet data after the packet data is read out from the packet memory based on a packet data identifier the controller sends to all of the two or more of the ports.

4 . The system of claim 3 , wherein each of the less than all of the two or more of the ports causes a different part of the packet data to be read out from the packet memory.

5 . The system of claim 4 , wherein the different part of the packet data of each of the less than all of the two or more of the ports is determined by the controller based on how the packet data is apportioned between the pages.

6 . The system of claim 5 , wherein a quantity of the less than all of the two or more of the ports is determined by the controller based on a quantity of the pages on which the packet data is stored.

7 . The system of claim 6 , wherein the controller selects the less than all of the two or more of the ports based on a congestion level of each of the two or more of the ports.

8 . The system of claim 7 , wherein each of the plurality of output ports comprise a buffer that stores a list identifying one or more packets that have been assigned to be output by the port by the controller, but have not yet been output by the port, and further wherein the congestion level of each of the two or more of the ports is based on a current quantity of packets identified by the list of the buffer of the port.

9 . The system of claim 7 , wherein the less than all of the two or more of the ports is exactly one of the two or more of the ports that causes all of the packet data to be read out from the packet memory.

10 . The system of claim 7 , wherein the less than all of the two or more ports is exactly a first port and a second port of the two or more of the ports, and further wherein the controller commands the first port to cause a first portion of the packet data to be read out and the second port to cause a remainder of the packet data that was not included within the first portion to be read out.

11 . The system of claim 10 , wherein the first portion is stored on one or more first pages of the pages mapped to the memory banks and includes the header of the packet data, and further wherein the remainder of the packet data is stored on one or more second pages of the pages mapped to the memory banks and includes the remainder of the packet data not included within the first pages.

12 . A controller stored on a non-transitory computer-readable medium and coupled with a plurality of output ports that selectively read and output packet data of a packet from a packet memory, wherein the packet memory has one or more memory banks storing the packet data, and further wherein the controller is configured to, if the packet data is to be output from two or more of the ports, command less than all of the two or more of the ports to cause the packet data to be read out from the packet memory and transmitted to all of the two or more of the ports.

13 . The controller of claim 12 , wherein the plurality of output ports and the controller are operating in a cut-thru mode such that each of the plurality of output ports begin to output packet data before the entirety of the packet has been received.

14 . The controller of claim 13 , wherein the controller is configured to command all of the two or more of the ports to listen for and output the packet data after the packet data is read out from the packet memory based on a packet data identifier the controller sends to all of the two or more of the ports.

15 . The controller of claim 14 , wherein each of the less than all of the two or more of the ports causes a different part of the packet data to be read out from the packet memory.

16 . The controller of claim 15 , wherein the packet data as stored on the memory banks is organized according to one or more pages mapped to the memory banks, further wherein the different part of the packet data of each of the less than all of the two or more of the ports is determined by the controller based on how the packet data is apportioned between the pages.

17 . The controller of claim 16 , wherein the controller is configured to determine a quantity of the less than all of the two or more of the ports based on a quantity of the pages on which the packet data is stored.

18 . The controller of claim 17 , wherein the controller is configured to select the less than all of the two or more of the ports based on a congestion level of each of the two or more of the ports.

19 . The controller of claim 18 , wherein each of the plurality of output ports comprise a buffer that stores a list identifying one or more packets that have been assigned to be output by the port by the controller, but have not yet been output by the port, and further wherein the congestion level of each of the two or more of the ports is based on a current quantity of packets identified by the list of the buffer of the port.

20 . The controller of claim 18 , wherein the less than all of the two or more of the ports is exactly one of the two or more of the ports that causes all of the packet data to be read out from the packet memory.

21 . The controller of claim 18 , wherein the less than all of the two or more ports is exactly a first port and a second port of the two or more of the ports, and further wherein the controller is configured to command the first port to cause a first portion of the packet data to be read out and the second port to cause a remainder of the packet data that was not included within the first portion to be read out.

22 . The controller of claim 21 , wherein the first portion is stored on one or more first pages of the pages mapped to the memory banks and includes the header of the packet data, and further wherein the remainder of the packet data is stored on one or more second pages of the pages mapped to the memory banks and includes the remainder of the packet data not included within the first pages.

23 . A method of operating a packet memory system, the method comprising:
storing packet data of a packet on one or more memory banks of a non-transitory computer-readable packet memory, wherein the storing of the packet data on the memory banks comprises organizing the packet data as

Assignees

• Xpliant Inc

Inventors

• Musoll Enrique

Classifications

• H04L49/103 Primary

  using a shared central buffer; using a shared memory · CPC title

• H04L12/1881

  with schedule organisation, e.g. priority, sequence management · CPC title

• H04L49/30

  Peripheral units, e.g. input or output ports · CPC title

• G06F12/0607 Primary

  Interleaved addressing · CPC title

• G06F2212/1044

  Space efficiency improvement · CPC title