Multicasting computer bus switch

Patent metadata

Field	Value
Publication number	US-2016147693-A1
Application number	US-201615010343-A
Country	US
Kind code	A1
Filing date	Jan 29, 2016
Priority date	Jan 5, 2004
Publication date	May 26, 2016
Grant date	—

Abstract

There is disclosed apparatus and methods of multicasting in a shared address space. A shared memory address space may include two or more multicast portions. Each multicast portion may be associated with a respective end point and with at least one other multicast portion. Data units may be transmitted to at least some of the end points via memory-mapped I/O into the shared memory address space. When a destination address of a data unit is in a first multicast portion associated with a first end point, the data unit may be transmitted to the first end point, revised to specify a destination address in a second multicast portion associated with the first multicast portion, and transmitted to a second end point associated with the second multicast portion.

First claim

1 - 19 . (canceled)

20 . A switch for multicasting, the switch comprising:
a first port providing a connection between the switch and a first end point; a second port providing a connection between the switch and a second end point; a buffer structured to receive and temporarily store data units having a destination address; a shared address space comprising:
a first gross address portion associated with the first end point, wherein the first gross address portion comprises:
a first individual portion unique to the first end point; and
a first multicast portion used for a first multicast group that includes the first end point and the second end point;

a second gross address portion associated with the second end point, wherein the second gross address portion comprises:
a second individual portion unique to the second end point; and
a second multicast portion used for a second multicast group that includes the second end point and at least one other end point; and

logic that causes a first data unit having a destination address in the first individual portion to be forwarded for transmission out the first port only and that causes a second data unit having a second destination address in the first multicast portion to be forwarded for transmission out of the first port and second port.

21 . The switch of claim 20 , wherein the at least one other end point includes the first end point and a third end point.

22 . The switch of claim 20 , wherein the at least one other end point includes a third end point and not the first end point.

23 . The switch of claim 20 , wherein the second data unit is transmitted out of the first and second port by employing the logic to execute the following:
causing the second data unit to be transmitted out of the first port; after the second data unit has been transmitted out of the first port, maintaining the second data unit in the buffer; replacing the second destination address of the second data unit with an address in the first multicast portion; and causing the second data unit with the address in the first multicast portion to be transmitted out of the second port.

24 . The switch of claim 20 , wherein the logic causes the first and second data units to be transmitted through the first port and the second port via a memory-mapped I/O into the shared memory address space.

25 . The switch of claim 20 , wherein the first port and the second port are connected with a PCI Express communication bus.

26 . The switch of claim 20 , wherein the first gross address portion further comprises a first broadcast portion used for a first broadcast group that includes all end points connected to the switch.

27 . The switch of claim 26 , wherein the first individual portion, the first multicast portion, and the first broadcast portion do not overlap with one another.

28 . The switch of claim 20 , wherein the shared address space is contiguous and wherein the first gross address space and second gross address space are contiguous.

29 . The switch of claim 20 , wherein the first gross address portion has a first size, wherein the second gross address portion has a second size, and wherein the first size is equal to the second size.

30 . A method of multicasting with a switch, the method comprising:
connecting a first port of the switch with a first end point; connecting a second port of the switch with a second end point; structuring a buffer of the switch to receive and temporarily store data units having a destination address; providing a shared address space with a first gross address portion and a second gross address portion, wherein the first gross address portion is associated with the first end point and comprises a first individual portion unique to the first end point as well as a first multicast portion used for a first multicast group that includes the first end point and a second end point, wherein the second gross address portion is associated with the second end point and comprises a second individual portion unique to the second end point as well as a second multicast portion used for a second multicast group; utilizing logic of the switch to cause a first data unit having a destination address in the first individual portion to be forwarded for transmission out of the first port only; and utilizing the logic of the switch to cause a second data unit having a second destination address in the first multicast portion to be forwarded for transmission out of the first port and the second port.

31 . The method of claim 30 , wherein the second multicast group includes the second end point and at least one other end point.

32 . The method of claim 30 , further comprising:
transmitting the second data unit out of the first port; after the second data unit has been transmitted out of the first port, storing the second data unit in the buffer; while the second data unit is stored in the buffer, replacing the second destination address of the second data unit with an address in the first multicast portion; transmitting the second data unit with the address in the first multicast portion out of the second port; and after the second data unit has been transmitted out of the second port, removing the second data unit from the buffer.

33 . The method of claim 30 , further comprising:
employing a memory-mapped I/O to transmit the first and second data units through the first and second ports, respectively, into the shared memory address space.

34 . The method of claim 30 , wherein the first port and second port are connected with a PCI Express communication bus.

35 . The method of claim 30 , wherein the first gross address portion further comprises a first broadcast portion used for a first broadcast group that includes all end points connected to the switch.

36 . The method of claim 35 , wherein the first broadcast portion does not overlap with the first multicast portion.

37 . The method of claim 30 , wherein a size of the first gross address portion is variable.

38 . A multicasting system, comprising:
a buffer structured to receive and store data units having a destination address; a shared address space comprising:
a first gross address portion associated with a first end point, wherein the first gross address portion comprises:
a first individual portion unique to the first end point; and
a first multicast portion used for a first multicast group that includes the first end point and a second end point;

a second gross address portion associated with the second end point, wherein the second gross address portion comprises:
a second individual portion unique to the second end point; and
a second multicast portion used for a second multicast group that includes the second end point and at least one other end point; and

logic that causes a first data unit having a destination address in the first individual portion to be transmitted to the first end point only and that causes a second data unit having a second destination address in the first multicast portion to be transmitted to both the first end point and the second end point.

39 . The system of claim 38 , further comprising:
a first port connected with the first end point; a second port connected with the second end point; and a PCI Express communication bus in communication with both the first port and the second port.

40 . A switch for multicasting, the switch comprising:
a buffer structured to receive and tempor

Assignees

• Avago Technologies General Ip

Inventors

• Stewart Heath
• De La Garrigue Michael
• Haywood Chris
• Reiner Thomas
• Wong Ken

Classifications

• H04L49/103

  using a shared central buffer; using a shared memory · CPC title

• H04L49/201

  Multicast operation; Broadcast operation · CPC title

• G06F13/404 Primary

  with address mapping · CPC title

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title