Level shifting circuit and method for the same

Patent metadata

Field	Value
Publication number	US-9825634-B2
Application number	US-201615209213-A
Country	US
Kind code	B2
Filing date	Jul 13, 2016
Priority date	Jul 24, 2015
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A level shifting circuit includes a transistor output unit that receives a first power supply signal and convert the first power supply signal to a second power supply signal having a different level from the first power supply signal and a current provision unit that provides a current to an output terminal of the transistor output unit when the first power supply signal of the transistor output unit is inputted to shorten a prolonged portion of the second power supply signal. Therefore, the level shifting circuit may provide an additional current to the output terminal of the transistor output unit to shorten a prolonged portion of the output voltage.

First claim

What is claimed is:

1. A level shifting circuit, comprising:
a transistor output unit that receives a first power supply signal, converts the first power supply signal to a second power supply signal having a different level from the first power supply signal to an output terminal, and outputs the second power supply signal; and
a current provision unit comprising a current mirror that generates a first current based on an input pulse signal to provide the first current to the output terminal of the transistor output unit when the first power supply signal is inputted to the transistor output unit, to shorten a prolonged portion of the second power supply signal.

2. The level shifting circuit of claim 1 , wherein the current provision unit receives the input pulse signal when the first power supply signal is inputted to the transistor output unit to provide the first current to the output terminal.

3. The level shifting circuit of claim 2 , wherein the input pulse signal has a first level for a predetermined time period when the first power supply signal is inputted.

4. The level shifting circuit of claim 2 , wherein the prolonged portion of the second power supply signal is shortened by an overlap of the first current and a second current according to the first power supply signal.

5. The level shifting circuit of claim 1 , wherein the current provision unit receives the input pulse signal for a predetermined time period when the first power supply signal is inputted to the transistor output unit, to provide the first current to the output terminal for the predetermined time period.

6. The level shifting circuit of claim 1 , wherein the current provision unit comprises a current output module having a current mirror structure, the current output module comprising a first terminal connected to an output terminal of the transistor output unit.

7. The level shifting circuit of claim 6 , wherein the current provision unit further comprises a block module connected to a second terminal of the current output module to prevent a gate oxide breakdown of the current output module.

8. The level shifting circuit of claim 7 , wherein the current provision unit further comprises a pulse input module that is connected to the block module and selectively turned on or off based on the input pulse signal to determine whether a current in respect of the output terminal of the transistor output unit is provided.

9. The level shifting circuit of claim 8 , wherein the block module is disposed between the current output module and the pulse input module to prevent a gate-source voltage of the current output module from exceeding a predetermined voltage.

10. The level shifting circuit of claim 1 , wherein the current provision unit is connected to the output terminal of the transistor output unit and is formed in a bilateral symmetric configuration with respect to the transistor output unit.

11. The level shifting circuit of claim 1 , wherein the transistor output unit includes a plurality of output transistors arranged to form a latch structure and to be controlled according to an inversion operation by the latch structure.

12. The level shifting circuit of claim 11 , wherein the transistor output unit further includes a plurality of block transistors connected to the plurality of output transistors to prevent a gate oxide breakdown of the plurality of output transistors.

13. The level shifting circuit of claim 12 , wherein the transistor output unit further includes a plurality of input transistors connected to the plurality of block transistors and selectively turned on or off based on the first power supply signal to control driving of the plurality of output transistors.

14. The level shifting circuit of claim 13 , wherein the plurality of block transistors are disposed between the plurality of output transistors and the plurality of input transistors to prevent a gate-source voltage of the plurality of output transistors from exceeding a predetermined voltage.

15. A level shifting method, comprising:
inputting a first power supply signal to a transistor output unit;
selectively inputting an input pulse signal to a current provision unit which comprises a current mirror is connected to an output terminal of the transistor output unit when the first power supply signal is inputted to the transistor output unit;
providing a first current to the output terminal based on the input pulse signal; and
overlapping the first current and a second current according to the first power supply signal to output a second power supply signal having a different level from the first power supply signal.

16. The level shifting method of claim 15 , wherein the input pulse signal has a first level for a predetermined time period when the first power supply signal is inputted to the transistor output unit.

17. The level shifting method of claim 15 , wherein the providing the first current includes providing the first current to the output terminal for a predetermined time period when the first power supply signal is inputted to the transistor output unit to shorten a prolonged portion of the second power supply signal.

18. A level shifting circuit, comprising:
a transistor output unit comprising an input terminal receiving a first power supply signal and an output terminal outputting a second power supply signal generated based on the first power supply signal, the second power supply signal having a different level from the first power supply signal and a prolonged portion; and
a current provision unit comprising a current mirror, connected and selectively providing a current to the output terminal of the transistor output unit based on a pulse signal when the first power supply signal is inputted to the transistor output unit,
wherein the current selectively provided to the output terminal of the transistor output unit shortens the prolonged portion of the second power supply signal, and
wherein the current provision unit is connected to the output terminal of the transistor output unit and is formed in a bilateral symmetric configuration with respect to the transistor output unit.

19. The level shifting circuit of claim 18 , wherein the current provision unit comprises:
a current output module connected to the output terminal of the transistor output unit;
a block module connected to the current output module to prevent a gate oxide breakdown of the current output module; and
a pulse input module connected to the block module and selectively turned on or off based on the pulse signal provided thereto.

20. The level shifting circuit of claim 18 , wherein the current provision unit comprises:
a plurality of output transistors arranged to form a latch structure;
a plurality of block transistors connected to the plurality of output transistors to prevent a gate oxide breakdown of the plurality of output transistors; and
a plurality of input transistors connected to the plurality of block transistors and selectively turned on or off based on the first power supply signal to control driving of the plurality of output transistors.

Assignees

• Magnachip Semiconductor Ltd

Inventors

• Hong Seok Min
• Kang Tae Kyoung
• Min jun sik

Classifications

• H03K3/356113 Primary

  using additional transistors in the input circuit · CPC title

• H03K19/018507 Primary

  Interface arrangements · CPC title