Voltage level shifter circuit

Patent metadata

Field	Value
Publication number	US-2016294394-A1
Application number	US-201615182486-A
Country	US
Kind code	A1
Filing date	Jun 14, 2016
Priority date	Nov 25, 2014
Publication date	Oct 6, 2016
Grant date	—

Abstract

Embodiments include apparatuses, methods, and systems for voltage level shifting a data signal between a low voltage domain and a high voltage domain. In embodiments, a voltage level shifter circuit may include adaptive keeper circuitry, enhanced interruptible supply circuitry, and/or capacitive boosting circuitry to reduce a minimum voltage of the low voltage domain that is supported by the voltage level shifter circuit. Other embodiments may be described and claimed.

First claim

1 - 20 . (canceled)

21 . A system comprising:
a first circuit block to operate in a first voltage domain; a second circuit block to operate in a second voltage domain; and a voltage level shifter circuit coupled to the first and second circuit blocks, wherein the voltage level shifter circuit is to receive an input signal in the first voltage domain and generate an output signal, based on the input signal, in the second voltage domain, and wherein the voltage level shifter circuit includes:
a data node to hold a logic state of the input signal;
a data bar node to hold a logic state of an input bar signal, the input bar signal being the inverse of the input signal; and
a keeper transistor having a source terminal coupled to the data node, a gate terminal coupled to the data bar node, and a drain terminal to receive the input bar signal.

22 . The system of claim 21 , wherein the keeper transistor is a first keeper transistor, and wherein the voltage level shifter circuit further comprises a second keeper transistor having a source terminal coupled to the data bar node, a gate terminal coupled to the data node, and a drain terminal to receive a delayed version of the input signal.

23 . The system of claim 22 , wherein the voltage level shifter circuit further includes:
a first firewall transistor coupled between the first keeper transistor and a ground terminal; and a second firewall transistor coupled between the second keeper transistor and the ground terminal, wherein a gate terminal of the second firewall transistor is coupled to a gate terminal of the first firewall transistor, and wherein the gate terminals of the first and second firewall transistors are to receive a firewall signal to selectively drive the data node and the data bar node to 0 Volts when the first voltage domain is power gated.

24 . The system of claim 21 , wherein the voltage level shifter circuit further includes:
a pull-down transistor coupled between the data node and a ground terminal, wherein a gate terminal of the pull-down transistor is to receive the input signal; an interruption transistor coupled to the data node, wherein a gate terminal of the interruption transistor is to receive the input signal; and a pull-up transistor coupled between the interruption transistor and a supply rail, wherein the supply rail is to receive a supply voltage.

25 . The system of claim 24 , wherein the pull-down transistor is a first pull-down transistor, and wherein the circuit further comprises a second pull-down transistor coupled between the ground terminal and an intermediate node that is between the pull-up transistor and the interruption transistor, wherein a gate terminal of the second pull-down transistor is to receive the input signal.

26 . The system of claim 25 , wherein the interruption transistor is a first interruption transistor, and wherein the voltage level shifter circuit further comprises:
a second interruption transistor coupled between the first interruption transistor and the pull-up transistor; and a third pull-down transistor coupled between the ground terminal and a second intermediate node that is between the pull-up transistor and the second interruption transistor, wherein a gate terminal of the third pull-down transistor is to receive the input signal.

27 . The system of claim 24 , wherein the voltage level shifter circuit further includes capacitive boosting circuitry to boost a voltage level of the input signal passed to the interruption transistor and the pull-down transistor.

28 . The system of claim 21 , wherein the data node is to hold the logic state of the input signal in the second voltage domain for generation of the output signal.

29 . The system of claim 21 , wherein the first circuit block, the second circuit block, and the voltage level shifter circuit are included in a processor of the system, and wherein the system further comprises a memory coupled to the processor.

30 . The system of claim 29 , further comprising a display coupled to the processor.

31 . The system of claim 21 , wherein the first circuit block and the second circuit block are disposed on different integrated circuit dies.

32 . A voltage level shifter circuit comprising:
an input node to receive an input data signal in a first voltage domain; a data node to hold a logic state of the input data signal for generation of an output signal that corresponds to the input signal and is in a second voltage domain that has a greater operating voltage than the first voltage domain; a first pull-down transistor coupled between the data node and a ground terminal, a gate terminal of the pull-down transistor to receive the input signal; an interruption transistor having a drain terminal coupled to the data node and a gate terminal to receive the input signal; and a second pull-down transistor coupled between the ground terminal and a source terminal of the interruption transistor, wherein a gate terminal of the second pull-down transistor is to receive the input signal.

33 . The circuit of claim 32 , further comprising a pull-up transistor coupled between the source terminal of the interruption transistor and a supply rail, the supply rail to receive a supply voltage associated with the second voltage domain.

34 . The circuit of claim 32 , wherein the interruption transistor is a first interruption transistor, and wherein the circuit further comprises:
a second interruption having a drain terminal coupled to the source terminal of the first interruption transistor; and a third pull-down transistor coupled between the ground terminal and a source terminal of the second interruption transistor, wherein a gate terminal of the third pull-down transistor is to receive the input signal.

35 . The circuit of claim 32 , further comprising:
a data bar node to hold a logic state of an input bar signal that is the inverse of the input signal; and a keeper transistor having a source terminal coupled to the data node, a gate terminal coupled to the data bar node, and a drain terminal to receive the input bar signal.

36 . The circuit of claim 35 , wherein the keeper transistor is a first keeper transistor, and wherein the circuit further comprises a second keeper transistor having a source terminal coupled to the data bar node, a gate terminal coupled to the data node, and a drain terminal to receive a delayed version of the input signal.

37 . The circuit of claim 32 , wherein the input node is a first input node, and wherein the circuit further comprises capacitive boosting circuitry that includes:
a p-type transistor coupled between a second input node and the first input node, wherein the second input node is to receive the data signal in the first voltage domain, and wherein a gate terminal of the first p-type transistor is to receive a delayed version of the data signal; an n-type transistor coupled between the first input node and the second input node, a gate terminal of the n-type transistor to receive a supply voltage associated with the first voltage domain; and a capacitive-coupled transistor coupled between the p-type transistor and the first input node, the capacitive-coupled transistor to charge the first input node to generate a boosted version of the data signal at the first input node.

38 . The circuit of claim 32 , further comprising an enable transistor coupled between the second pull-down transistor and the ground terminal, the gate terminal of the enable transistor to receive an enable signal to selectively enable an enha

Assignees

• Intel Corp

Inventors

• Trivedi Amit R
• Kulkarni Jaydeep P
• Tokunaga Carlos
• Khellah Muhammad M
• Tschanz James W

Classifications

• H03K19/018521 Primary

  of complementary type, e.g. CMOS · CPC title

• H03K3/356113 Primary

  using additional transistors in the input circuit · CPC title