Low-ripple latch circuit for reducing short-circuit current effect

Patent metadata

Field	Value
Publication number	US-2016336927-A1
Application number	US-201615044114-A
Country	US
Kind code	A1
Filing date	Feb 16, 2016
Priority date	May 14, 2015
Publication date	Nov 17, 2016
Grant date	—

Abstract

A latch circuit includes an input stage, an amplifying stage and a clock gating circuit. The input stage is arranged for receiving at least a clock signal and a data control signal. The amplifying stage is coupled to the input stage and supplied by a supply voltage and a ground voltage, and is arranged for retaining a data value and outputting the data value according to the clock signal and the data control signal. The clock gating circuit is coupled to the amplifying stage, and is arranged for avoiding a short-circuit current between the supply voltage and the ground voltage.

First claim

1 . A latch circuit, comprising:
an input stage, for receiving at least a clock signal and a data control signal; an amplifying stage, coupled to the input stage and supplied by a supply voltage and a ground voltage, for outputting a data value according to the clock signal and the data control signal; and a clock gating circuit, coupled to the amplifying stage, for disconnecting a path between the supply voltage and the ground voltage while the clock signal has a state transition; wherein the amplifying stage comprises: a first N-type metal-oxide-semiconductor (NMOS) and a second NMOS, wherein source electrodes of the first NMOS and the second NMOS are coupled to the ground voltage; a first P-type metal-oxide-semiconductor (PMOS) and a second PMOS, wherein source electrodes of the first PMOS and the second PMOS are coupled to the supply voltage; and a differential output terminals comprising a first output terminal and a second output terminal, wherein the first output terminal is electrically connected to gate electrodes of the first NMOS and the first PMOS, and the second output terminal is electrically connected to gate electrodes of the second NMOS and the second PMOS; wherein the clock gating circuit is arranged to selectively connect the first output terminal to drain electrodes of the second NMOS and the second PMOS or not, and to selectively connect the second output terminal to drain electrodes of the first NMOS and the first PMOS or not.

2 . The latch circuit of claim 1 , wherein the clock gating circuit is arranged for disconnecting the path while the clock signal has the state transition to avoid the short-circuit current flowing through the supply voltage, the amplifying stage, the input stage and the ground voltage.

3 . The latch circuit of claim 1 , wherein the clock gating circuit comprises a plurality of switches controlled by the clock signal.

4 . (canceled)

5 . The latch circuit of claim 1 , wherein the clock gating circuit comprises a plurality of switches, wherein at least a portion of the switches are coupled between the first PMOS and the second output terminal and coupled between the second PMOS and the first output terminal, and the portion of the switches are controlled by the clock signal.

6 . The latch circuit of claim 5 , wherein another portion of the switches are coupled between the first NMOS and the second output terminal and coupled between the second NMOS and the first output terminal, and said another portion of the switches are controlled by an inverted signal of the clock signal.

7 . The latch circuit of claim 5 , wherein the input stage comprises:
a first input NMOS and a second input NMOS connected in cascode and coupled between the second output terminal and the ground voltage, wherein the first input NMOS and the second input NMOS are controlled by the data control signal and the clock signal, respectively; and a third input NMOS and a fourth input NMOS connected in cascode and coupled between the first output terminal and the ground voltage, wherein the third input NMOS and the fourth input NMOS are controlled by an inverted signal of the data control signal and the clock signal, respectively.

8 . The latch circuit of claim 7 , wherein when the clock signal changes from a low voltage to a high voltage, the portion of the switches are turned off before the first input NMOS turns on.

9 . The latch circuit of claim 1 , wherein the amplifying stage is arranged to output the data value and a corresponding inverted data value according to the clock signal and the data control signal, and the latch circuit further comprises:
a crossing point control circuit, coupled to the input stage and the amplifying stage, for controlling a crossing point of the data value and the corresponding inverted data value to be not at a middle voltage while the data value changes.

10 . The latch circuit of claim 9 , wherein a size of at least one transistor within the crossing point control circuit is different from a size of at least one transistor within the input stage.

11 . The latch circuit of claim 9 , wherein the input stage comprises:
a first input NMOS and a second input NMOS connected in cascode and coupled between the second output terminal and the ground voltage, wherein the first input NMOS and the second input NMOS are controlled by the data control signal and the clock signal, respectively; and a third input NMOS and a fourth input NMOS connected in cascode and coupled between the first output terminal and the ground voltage, wherein the third input NMOS and the fourth input NMOS are controlled by an inverted signal of the data control signal and the clock signal, respectively; and the crossing point control circuit comprises:
a first control PMOS and a second control PMOS connected in cascode and coupled between the second output terminal and the supply voltage, wherein the first control PMOS and the second control PMOS are controlled by the data control signal and an inverted signal of the clock signal, respectively; and
a third control PMOS and a fourth control PMOS connected in cascode and coupled between the first output terminal and the supply voltage, wherein the third control PMOS and the fourth control PMOS are controlled by the inverted signal of the data control signal and the inverted signal of the clock signal, respectively.

12 . The latch circuit of claim 11 , wherein a size of at least one of the first control PMOS and the third control PMOS is different from a size of at least one of the first input NMOS and the third input NMOS.

13 . The latch circuit of claim 9 , wherein the latch circuit is applied to a digital to analog converter (DAC); and when the amplifying stage is arranged to output the data value and the corresponding inverted data value to P-type switches of the DAC, the crossing point of the data value and the corresponding inverted data value is lower than the middle voltage while the data value changes; and when the amplifying stage is arranged to output the data value and the corresponding inverted data value to N-type switches of the DAC, the crossing point of the data value and the corresponding inverted data value is higher than the middle voltage while the data value changes.

14 . A latch circuit, comprising:
an input stage, for receiving at least a clock signal and a data control signal; an amplifying stage, coupled to the input stage and supplied by a supply voltage and a ground voltage, for outputting a data value and a corresponding inverted data value according to the clock signal and the data control signal; and a crossing point control circuit, coupled to the input stage and the amplifying stage, for controlling a crossing point of the data value and the corresponding inverted data value to be not at a middle voltage while the data value changes; wherein the input stage comprises: a first input NMOS and a second input NMOS connected in cascode and coupled between the second output terminal and the ground voltage, wherein the first input NMOS and the second input NMOS are controlled by the data control signal and the clock signal, respectively; and a third input NMOS and a fourth input NMOS connected in cascode and coupled between the first output terminal and the ground voltage, wherein the third input NMOS and the fourth input NMOS are controlled by an inverted signal of the data control signal and the clock signal, respectively; and the crossing point control circuit comprises:
a first control PMOS and a second control PMOS connected in cascode and coupled between the second output terminal and the supply voltage, wherein the first c

Assignees

• Mediatek Inc

Inventors

• Ho Chen-Yen
• Lin Yu-Hsin

Classifications

• H03K3/356191

  with synchronous operation · CPC title

• H03K3/356113 Primary

  using additional transistors in the input circuit · CPC title

• H03M1/0872

  by disabling changes in the output during the transitions, e.g. by holding or latching · CPC title

• H03M1/66 Primary

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03K3/356121 Primary

  with synchronous operation (H03K3/35613, H03K3/356147 take precedence) · CPC title