Semiconductor device and electronic device

Patent metadata

Field	Value
Publication number	US-9825526-B2
Application number	US-201615350516-A
Country	US
Kind code	B2
Filing date	Nov 14, 2016
Priority date	Sep 3, 2012
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

To reduce a variation in the electrical characteristics of a transistor. A potential generated by a voltage converter circuit is applied to a back gate of a transistor included in a voltage conversion block. Since the back gate of the transistor is not in a floating state, a current flowing through the back channel can be controlled so as to reduce a variation in the electrical characteristics of the transistor. Further, a transistor with low off-state current is used as the transistor included in the voltage conversion block, whereby storage of the output potential is controlled.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor;
a first capacitor;
a second capacitor; and
a third capacitor,
wherein each of the first transistor and the third transistor comprises a channel formation region comprising an oxide semiconductor,
wherein the second transistor comprises a channel formation region comprising silicon,
wherein a gate of the first transistor is directly connected to one of a source and a drain of the first transistor,
wherein a back gate of the first transistor is directly connected to the one of the source and the drain of the first transistor,
wherein the one of the source and the drain of the first transistor is directly connected to the first capacitor,
wherein a gate of the second transistor is directly connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the first transistor,
wherein the one of the source and the drain of the second transistor is directly connected to a first electrode of the second capacitor,
wherein a second electrode of the second capacitor is supplied with a first clock signal,
wherein one of a source and a drain of the third transistor is directly connected to the third capacitor, and
wherein a back gate of the third transistor is electrically connected to the one of the source and the drain of the first transistor.

2. The semiconductor device according to claim 1 ,
wherein a memory circuit comprises the third transistor and the third capacitor.

3. The semiconductor device according to claim 2 ,
wherein the memory circuit is a part of a register of a CPU core.

4. The semiconductor device according to claim 1 ,
wherein a voltage converter circuit comprises the first transistor, the first capacitor, the second transistor and the second capacitor, and
wherein the voltage converter circuit is configured to generate a potential by using the first clock signal.

5. The semiconductor device according to claim 1 ,
wherein the second transistor is an n-channel transistor.

6. The semiconductor device according to claim 1 , further comprising:
a fourth transistor; and
a fourth capacitor,
wherein a gate of the fourth transistor is directly connected to one of a source and a drain of the fourth transistor,
wherein the one of the source and the drain of the fourth transistor is directly connected to the other of the source and the drain of the second transistor,
wherein the one of the source and the drain of the fourth transistor is directly connected to a first electrode of the fourth capacitor, and
wherein a second electrode of the fourth capacitor is supplied with a second clock signal.

7. A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor;
a first capacitor;
a second capacitor; and
a third capacitor,
wherein each of the first transistor, the second transistor and the third transistor comprises a channel formation region comprising an oxide semiconductor,
wherein a gate of the first transistor is directly connected to one of a source and a drain of the first transistor,
wherein a back gate of the first transistor is directly connected to the one of the source and the drain of the first transistor,
wherein the one of the source and the drain of the first transistor is directly connected to the first capacitor,
wherein a gate of the second transistor is directly connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the first transistor,
wherein the one of the source and the drain of the second transistor is directly connected to a first electrode of the second capacitor,
wherein a second electrode of the second capacitor is supplied with a first clock signal,
wherein one of a source and a drain of the third transistor is directly connected to the third capacitor, and
wherein a back gate of the third transistor is electrically connected to the one of the source and the drain of the first transistor.

8. The semiconductor device according to claim 7 ,
wherein a memory circuit comprises the third transistor and the third capacitor.

9. The semiconductor device according to claim 8 ,
wherein the memory circuit is a part of a register of a CPU core.

10. The semiconductor device according to claim 7 ,
wherein a voltage converter circuit comprises the first transistor, the first capacitor, the second transistor and the second capacitor, and
wherein the voltage converter circuit is configured to generate a potential by using the first clock signal.

11. The semiconductor device according to claim 7 ,
wherein the second transistor is an n-channel transistor.

12. The semiconductor device according to claim 7 , further comprising:
a fourth transistor; and
a fourth capacitor,
wherein a gate of the fourth transistor is directly connected to one of a source and a drain of the fourth transistor,
wherein the one of the source and the drain of the fourth transistor is directly connected to the other of the source and the drain of the second transistor,
wherein the one of the source and the drain of the fourth transistor is directly connected to a first electrode of the fourth capacitor, and
wherein a second electrode of the fourth capacitor is supplied with a second clock signal.

13. A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor;
a first capacitor;
a second capacitor; and
a third capacitor,
wherein the first transistor comprises a channel formation region comprising an oxide semiconductor,
wherein a gate of the first transistor is directly connected to one of a source and a drain of the first transistor,
wherein a back gate of the first transistor is directly connected to the one of the source and the drain of the first transistor,
wherein the one of the source and the drain of the first transistor is directly connected to the first capacitor,
wherein a gate of the second transistor is directly connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the first transistor,
wherein the one of the source and the drain of the second transistor is directly connected to a first electrode of the second capacitor,
wherein a second electrode of the second capacitor is supplied with a first clock signal,
wherein one of a source and a drain of the third transistor is directly connected to the third capacitor, and
wherein a back gate of the third transistor is electrically connected to the one of the source and the drain of the first transistor.

14. The semiconductor device according to claim 13 ,
wherein a memory circuit comprises the third transistor and the third capacitor.

15. The semiconductor device according to claim 14 ,
wherein the memory circuit is a part of a register of a CPU core.

16. The semiconductor device according to claim 13 ,
wherein a voltage converter circuit comprises the first transistor, the first capacitor, the second transistor and the second capacitor, and
wherein the voltage converter circuit is configured to generate a potential by using the first clock signal.

17. The semiconductor device according to claim 13 ,

Assignees

• Semiconductor Energy Lab

Inventors

• Watanabe Kazunori

Classifications

• G06F1/3234 Primary

  Power saving characterised by the action undertaken · CPC title

• G05F3/205

  Substrate bias-voltage generators (for static stores G11C5/146) · CPC title

• G11C5/146

  Substrate bias generators (G11C5/141 takes precedence) · CPC title

• Y02B60/1282

  Cross-Sectional Technologies · mapped topic

• H02M3/073

  Charge pumps of the Schenkel-type · CPC title