Semiconductor device

Patent metadata

Field	Value
Publication number	US-9312280-B2
Application number	US-201514801347-A
Country	US
Kind code	B2
Filing date	Jul 16, 2015
Priority date	Jul 25, 2014
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A semiconductor device capable of retaining data for a long time is provided. The semiconductor device includes first to third transistors, a fourth transistor including first and second gates, first to third nodes, a capacitor, and an input terminal. A source of the first transistor is connected to the input terminal. A drain of the first transistor and a source of the second transistor are connected to the first node. A gate of the second transistor, a drain of the second transistor, and a source of the third transistor are connected to the second node. A gate of the third transistor, a drain of the third transistor, the capacitor, and the second gate of the fourth transistor are connected to the third node.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor including a first gate and a second gate;
a capacitor; and
an input terminal,
wherein a gate of the first transistor is electrically connected to a third node,
wherein one of a source and a drain of the first transistor is electrically connected to the input terminal,
wherein the other of the source and the drain of the first transistor is electrically connected to a first node,
wherein a gate of the second transistor is electrically connected to a second node,
wherein one of a source and a drain of the second transistor is electrically connected to the first node,
wherein the other of the source and the drain of the second transistor is electrically connected to the second node,
wherein a gate of the third transistor is electrically connected to the third node,
wherein one of a source and a drain of the third transistor is electrically connected to the second node,
wherein the other of the source and the drain of the third transistor is electrically connected to the third node,
wherein a first terminal of the capacitor is electrically connected to the third node,
wherein the second gate is electrically connected to the third node, and
wherein the first gate and the second gate overlap with each other with a semiconductor layer therebetween.

2. The semiconductor device according to claim 1 ,
wherein the first transistor further includes a third gate,
wherein the third transistor further includes a fourth gate,
wherein the second transistor further includes a fifth gate, and
wherein the third gate, the fourth gate, and the fifth gate are electrically connected to the third node.

3. The semiconductor device according to claim 1 , wherein each of the first to third transistors is an n-channel transistor.

4. The semiconductor device according to claim 1 , wherein each of the first to third transistors includes an oxide semiconductor in a channel.

5. The semiconductor device according to claim 4 , wherein the oxide semiconductor contains indium, zinc, and M, where M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf.

6. A storage device comprising the semiconductor device according to claim 1 and a storage element.

7. A register circuit comprising the semiconductor device according to claim 1 .

8. A display device comprising the semiconductor device according to claim 1 and a display element.

9. An electronic device comprising the semiconductor device according to claim 1 and at least one of a microphone, a speaker, a display portion, and an operation key.

10. A semiconductor device comprising:
a first transistor including a first gate and a second gate;
a second transistor including a third gate and a fourth gate;
a third transistor including a fifth gate and a sixth gate;
a capacitor;
an input terminal; and
a memory cell comprising a fourth transistor including a seventh gate and a eighth gate,
wherein one of a source and a drain of the first transistor is electrically connected to the input terminal,
wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein one of a source and a drain of the third transistor is electrically connected to the third gate and the other of the source and the drain of the second transistor, and
wherein the first gate, the second gate, the fourth gate, the fifth gate, the sixth gate, the seventh gate, the other of the source and the drain of the third transistor, and a first terminal of the capacitor are electrically connected to each other.

11. The semiconductor device according to claim 10 , wherein each of the first to third transistors is an n-channel transistor.

12. The semiconductor device according to claim 10 , wherein each of the first to third transistors includes an oxide semiconductor in a channel.

13. The semiconductor device according to claim 12 , wherein the oxide semiconductor contains indium, zinc, and M, where M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf.

14. A storage device comprising the semiconductor device according to claim 10 and a storage element.

15. A register circuit comprising the semiconductor device according to claim 10 .

16. A display device comprising the semiconductor device according to claim 10 and a display element.

17. An electronic device comprising the semiconductor device according to claim 10 , and at least one of a microphone, a speaker, a display portion, and an operation key.

Assignees

• Semiconductor Energy Lab

Inventors

• Kobayashi Hidetomo

Classifications

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D62/80

  characterised by the materials · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title