Semiconductor device and electronic device

Patent metadata

Field	Value
Publication number	US-9501119-B2
Application number	US-201514608844-A
Country	US
Kind code	B2
Filing date	Jan 29, 2015
Priority date	Sep 3, 2012
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

To reduce a variation in the electrical characteristics of a transistor. A potential generated by a voltage converter circuit is applied to a back gate of a transistor included in a voltage conversion block. Since the back gate of the transistor is not in a floating state, a current flowing through the back channel can be controlled so as to reduce a variation in the electrical characteristics of the transistor. Further, a transistor with low off-state current is used as the transistor included in the voltage conversion block, whereby storage of the output potential is controlled.

First claim

What is claimed is:

1. A semiconductor device comprising:
a power source circuit comprising:
a voltage converter circuit configured to generate a potential by using a first clock signal, the voltage converter circuit comprising a first transistor; and

a CPU core comprising:
a register comprising:
a selector;
a first memory circuit configured to store data, the first memory circuit being supplied with a second clock signal; and
a second memory circuit configured to store the data output from the first memory circuit, the second memory circuit comprising a second transistor and a first capacitor,

wherein an output terminal of the selector is electrically connected to an input terminal of the first memory circuit,
wherein an input terminal of the selector is electrically connected to an output terminal of the second memory circuit,
wherein each of the first transistor and the second transistor comprises a channel formation region comprising an oxide semiconductor,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the first transistor,
wherein a back gate of the first transistor is electrically connected to the one of the source and the drain of the first transistor,
wherein one of a source and a drain of the second transistor is electrically connected to the first capacitor, and
wherein a back gate of the second transistor is supplied with the potential.

2. The semiconductor device according to claim 1 ,
wherein an output terminal of the voltage converter circuit is electrically connected to the one of the source and the drain of the first transistor.

3. The semiconductor device according to claim 2 ,
wherein the voltage converter circuit further comprises a second capacitor,
wherein a first electrode of the second capacitor is electrically connected to the other of the source and the drain of the first transistor, and
wherein a second electrode of the second capacitor is supplied with the first clock signal.

4. The semiconductor device according to claim 3 ,
wherein the first electrode of the second capacitor is electrically connected to the other of the source and the drain of the first transistor via at least a third capacitor.

5. The semiconductor device according to claim 1 ,
wherein an output terminal of the voltage converter circuit is electrically connected to the other of the source and the drain of the first transistor.

6. The semiconductor device according to claim 5 ,
wherein the back gate of the first transistor is electrically connected to the one of the source and the drain of the first transistor via at least a third transistor.

7. The semiconductor device according to claim 5 ,
wherein the voltage converter circuit further comprises a second capacitor,
wherein a first electrode of the second capacitor is electrically connected to the one of the source and the drain of the first transistor, and
wherein a second electrode of the second capacitor is supplied with the first clock signal.

8. The semiconductor device according to claim 7 ,
wherein the first electrode of the second capacitor is electrically connected to the one of the source and the drain of the first transistor via at least a third capacitor.

9. A semiconductor device comprising:
a power source circuit comprising:
a first voltage converter circuit configured to generate a first potential by using a first clock signal, the first voltage converter circuit comprising a first transistor; and
a second voltage converter circuit configured to generate a second potential by using a second clock signal, the second voltage converter circuit comprising a second transistor; and

a CPU core comprising:
a register comprising:
a first memory circuit configured to store data, the first memory circuit being supplied with a third clock signal; and
a second memory circuit configured to store the data output from the first memory circuit, the second memory circuit comprising a third transistor and a first capacitor,

wherein a gate of the first transistor is electrically connected to one of a source and a drain of the first transistor,
wherein a back gate of the first transistor is electrically connected to the one of the source and the drain of the first transistor,
wherein a gate of the second transistor is electrically connected to one of a source and a drain of the second transistor,
wherein a back gate of the second transistor is electrically connected to the one of the source and the drain of the second transistor,
wherein one of a source and a drain of the third transistor is electrically connected to the first capacitor, and
wherein a back gate of the third transistor is supplied with the first potential or the second potential.

10. The semiconductor device according to claim 9 ,
wherein each of the first transistor, the second transistor and the third transistor comprises a channel formation region comprising an oxide semiconductor.

11. The semiconductor device according to claim 9 ,
wherein an output terminal of the first voltage converter circuit is electrically connected to the one of the source and the drain of the first transistor, and
wherein an output terminal of the second voltage converter circuit is electrically connected to the other of the source and the drain of the second transistor.

12. The semiconductor device according to claim 11 ,
wherein the back gate of the second transistor is electrically connected to the one of the source and the drain of the second transistor via at least a fourth transistor.

13. The semiconductor device according to claim 11 ,
wherein the first voltage converter circuit further comprises a second capacitor,
wherein the second voltage converter circuit further comprises a third capacitor,
wherein a first electrode of the second capacitor is electrically connected to the other of the source and the drain of the first transistor,
wherein a second electrode of the second capacitor is supplied with the first clock signal,
wherein a first electrode of the third capacitor is electrically connected to the one of the source and the drain of the second transistor, and
wherein a second electrode of the second capacitor is supplied with the second clock signal.

14. The semiconductor device according to claim 13 ,
wherein the first electrode of the second capacitor is electrically connected to the other of the source and the drain of the first transistor via at least a fourth capacitor, and
wherein the first electrode of the third capacitor is electrically connected to the one of the source and the drain of the second transistor via at least a fifth capacitor.

15. A semiconductor device comprising:
a power source circuit comprising:
a first voltage converter circuit configured to generate a first potential, the first voltage converter circuit comprising a first transistor; and
a second voltage converter circuit configured to generate a second potential, the second voltage converter circuit comprising a second transistor;

an oscillator configured to output a clock signal to the power source circuit; and
a CPU core configured to control whether an operation of the oscillator is stopped or not, the CPU core comprising:
a register comprising:
a first memory circuit configured to store data in a period during which a power source voltage is applied to the CPU core; and
a second memory circuit configured to store data in a period during which supply of the power source voltage to the CPU core is stopped, the second memory circuit comprising a third transistor and a first capacitor,

Assignees

• Semiconductor Energy Lab

Inventors

• Watanabe Kazunori

Classifications

• G06F1/3234 Primary

  Power saving characterised by the action undertaken · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M3/073

  Charge pumps of the Schenkel-type · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title