Plasma etching of solder resist openings

Patent metadata

Field	Value
Publication number	US-9820386-B2
Application number	US-201615074064-A
Country	US
Kind code	B2
Filing date	Mar 18, 2016
Priority date	Mar 18, 2016
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A method of forming an electronic assembly. The method includes covering a patterned conductive layer that is on a dielectric layer with a solder resist; depositing a metal layer on to the solder resist; depositing a photo resist onto the metal layer; patterning the photo resist; etching the metal layer that is exposed from the photo resist to form a metal mask; removing the photo resist; and plasma etching the solder resist that is exposed from the metal mask. An electronic assembly for securing for an electronic card. The electronic assembly includes a patterned conductive layer that is on a dielectric layer; and a solder resist covering the patterned conductive layer and the dielectric layer, wherein the solder resist includes openings that expose the patterned conductive layer, wherein the openings in the solder resist only have organic material on side walls of the respective openings.

First claim

What is claimed is:

1. A method of forming an electronic assembly comprising:
covering a patterned conductive layer that is on a dielectric layer with a solder resist;
forming a metal mask on the solder resist;
plasma etching the solder resist that is exposed from the metal mask; and
removing the entire metal mask.

2. The method of claim 1 wherein forming a metal mask on the solder resist includes depositing a metal layer on to the solder resist.

3. The method of claim 2 wherein forming a metal mask on the solder resist includes depositing a photo resist onto the metal layer.

4. The method of claim 3 wherein forming a metal mask on the solder resist includes patterning the photo resist.

5. The method of claim 4 wherein forming a metal mask on the solder resist includes etching the metal layer that is exposed from the photo resist to form the metal mask.

6. The method of claim 5 wherein forming a metal mask on the solder resist includes removing the photo resist after etching the metal layer.

7. The method of claim 1 wherein plasma etching the solder that is exposed from the metal mask includes forming openings in the solder resist.

8. The method of claim 7 wherein forming openings in the solder resist includes forming different size openings in the solder resist.

9. The method of claim 7 wherein forming openings in the solder resist includes forming openings that are less than 25 microns in diameter and additional openings that are less than 50 microns.

10. The method of claim 1 wherein plasma etching the solder resist that is exposed from the metal mask includes reactive ion etching the solder resist.

11. The method of claim 1 wherein plasma etching the solder resist that is exposed from the metal mask includes using fluorine and oxygen containing plasma to etch the solder resist.

12. A method of forming an electronic assembly comprising:
covering a patterned conductive layer that is on a dielectric layer with a solder resist;
depositing a metal layer on to the solder resist;
depositing a photo resist onto the metal layer;
patterning the photo resist;
etching the metal layer that is exposed from the photo resist to form a metal mask;
removing the photo resist;
plasma etching the solder resist that is exposed from the metal mask; and
removing the entire metal mask.

13. The method of claim 12 wherein plasma etching the solder resist that is exposed from the metal mask includes forming openings in the solder resist, wherein forming openings in the solder resist includes forming different size openings in the solder resist where some of the openings are less than 25 microns in diameter.

14. The method of claim 12 wherein plasma etching the solder resist that is exposed from the metal mask includes reactive ion etching the solder resist using fluorine and oxygen containing plasma to etch the solder resist.

Assignees

• Intel Corp

Inventors

• Darmawikarta Kristof
• Jain Rahul
• May Robert Alan
• Li Sheng
• Boyapati Sri Ranga Sai

Classifications

• H05K2203/0562

  Details of resist · CPC title

• H05K2203/0548

  Masks · CPC title

• H05K2203/0588

  Second resist used as pattern over first resist · CPC title

• H05K1/0313

  Organic insulating material · CPC title

• H05K3/3452

  Solder masks · CPC title