Imprinted bi-layer micro-structure method

US9277642B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9277642-B2
Application numberUS-201314012216-A
CountryUS
Kind codeB2
Filing dateAug 28, 2013
Priority dateMar 5, 2013
Publication dateMar 1, 2016
Grant dateMar 1, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of making an imprinted micro-wire structure includes providing a substrate having an edge area and a central area separate from the edge area and providing first, second, and third different stamps. A curable bottom, connecting layer, and top layer are formed on the substrate. A bottom-layer micro-channel is imprinted in the bottom layer in the central area and the edge area, a connecting-layer micro-channel is imprinted in the connecting layer in the edge area over the bottom-layer micro-channel, an edge micro-channel is imprinted in the top layer in the edge area over the connecting-layer micro-channel, and top-layer micro-channels are imprinted in the top layer over the central area. Micro-wires are formed in each micro-channel. The bottom-layer micro-wire in the central area is electrically connected to the edge micro-wire in the edge area and is electrically isolated from the top-layer micro-wire.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method of making a micro-wire structure, comprising: providing a substrate having an edge area and a central area separate from the edge area; providing first, second, and third different stamps; providing a curable bottom layer in relation to the substrate; forming an imprinted bottom-layer micro-channel in the curable bottom layer by at least imprinting the curable bottom layer with the first stamp in at least a portion of the central area and in at least a portion of the edge area and curing the curable bottom layer, the bottom-layer micro-channel extending from the central area into the edge area; locating a curable electrical conductor in the bottom-layer micro-channel and curing the curable electrical conductor to form a bottom-layer micro-wire in the bottom-layer micro-channel, the bottom-layer micro-wire extending from the central area into the edge area; providing a curable connecting layer adjacent to and in contact with the cured bottom layer and the bottom-layer micro-wire; forming an imprinted connecting-layer micro-channel in the curable connecting layer by at least imprinting the curable connecting layer with the second stamp over at least a portion of the bottom-layer micro-channel in at least a portion of the edge area and curing the curable connecting layer; forming a connecting-layer micro-wire in the connecting-layer micro-channel contacting at least a portion of the bottom-layer micro-wire; providing a curable top layer adjacent to and in contact with the cured connecting layer and the connecting-layer micro-wire; forming an imprinted edge micro-channel in the curable top layer by at least imprinting the curable top layer with the third stamp over at least a portion of the connecting-layer micro-channel in at least a portion of the edge area and forming an imprinted top-layer micro-channel in the curable top layer by at least imprinting the curable top layer with the third stamp separate from the bottom-layer micro-channel and over at least a portion of the bottom-layer micro-channel in at least a portion of the central area and curing the curable top layer; forming an edge micro-wire in the edge micro-channel contacting at least a portion of the connecting-layer micro-wire and forming a top-layer micro-wire in the top-layer micro-channel that is electrically isolated from the edge micro-wire, the connecting-layer micro-wire, and the bottom-layer micro-wire; and wherein the bottom-layer micro-wire in the central area is electrically connected to the edge micro-wire in the edge area and is electrically isolated from the top-layer micro-wire. 2. The method of claim 1 , wherein the substrate has at least one edge and the edge area is adjacent to the edge. 3. The method of claim 1 , wherein the step of forming the imprinted connecting-layer micro-channel further includes contacting the bottom-layer micro-wire with the second stamp. 4. The method of claim 1 , wherein the step of forming the imprinted edge micro-channel further includes contacting the connecting-layer micro-wire with the third stamp. 5. The method of claim 1 , wherein the bottom and connecting layers include cross-linkable material and further including cross linking the cross-linkable first-layer material to the cross-linkable second-layer material or wherein the connecting and top layers include cross-linkable material and further including cross linking the cross-linkable second-layer material to the cross-linkable third-layer material. 6. The method of claim 1 , wherein a portion of the edge micro-wire forms at least a portion of a connection pad. 7. The method of claim 6 , wherein the connection pad further includes a plurality of micro-wires. 8. The method of claim 1 , further including forming a plurality of edge micro-wires electrically connected through a corresponding plurality of connection micro-wires to a corresponding plurality of bottom-layer micro-wires. 9. The method of claim 8 , further including forming a plurality of top-layer micro-wires electrically isolated from the edge micro-wires. 10. The method of claim 1 , further including removing a portion of the cured connecting layer or removing a portion of the cured top layer. 11. The method of claim 10 , further including removing the portion of the cured second or cured top layer by treating the cured second or cured top layer with a plasma treatment. 12. The method of claim 10 , further including thinning the cured second or cured top layer by a thinning depth. 13. The method of claim 12 , wherein the thinning depth is less than the difference between the depth of the cured second or cured top layer and the depth of any micro-channels in the corresponding cured second or cured top layer. 14. A method of making a micro-wire structure, comprising: providing a substrate having an edge area and a central area separate from the edge area; providing first, second, and third different stamps; providing a curable bottom layer in relation to the substrate; forming an imprinted bottom-layer micro-channel in the curable bottom layer by at least imprinting the curable bottom layer with the first stamp in at least a portion of the central area and in at least a portion of the edge area and curing the curable bottom layer, the bottom-layer micro-channel extending from the central area into the edge area; locating a curable electrical conductor in the bottom-layer micro-channel and curing the curable electrical conductor to form a bottom-layer micro-wire in the bottom-layer micro-channel, the bottom-layer micro-wire extending from the central area into the edge area; providing a curable connecting layer adjacent to and in contact with the cured bottom layer and the bottom-layer micro-wire; forming an imprinted connecting-layer micro-channel in the curable connecting layer by at least imprinting the curable connecting layer with the second stamp over at least a portion of the bottom-layer micro-channel in at least a portion of the edge area and curing the curable connecting layer; forming a connecting-layer micro-wire in the connecting-layer micro-channel contacting at least a portion of the bottom-layer micro-wire; providing a curable top layer adjacent to and in contact with the cured connecting layer and the connecting-layer micro-wire; forming an imprinted edge micro-channel in the curable top layer by at least imprinting the curable top layer with the third stamp over at least a portion of the connecting-layer micro-channel in at least a portion of the edge area and forming an imprinted top-layer micro-channel in the curable top layer by at least imprinting the curable top layer with the third stamp separate from the bottom-layer micro-channel and over at least a portion of the bottom-layer micro-channel in at least a portion of the central area and curing the curable top layer; forming an edge micro-wire in the edge micro-channel contacting at least a portion of the connecting-layer micro-wire and forming a top-layer micro-wire in the top-layer micro-channel that is electrically isolated from the edge micro-wire, the connecting-layer micro-wire, and the bottom-layer micro-wire; forming a plurality of edge micro-wires electrically connected through a corresponding plurality of connection micro-wires to a corresponding plurality of bottom-layer micro-wires; forming a plurality of top-layer micro-wires electrically isolated from the edge micro-wires; wherein the bottom-layer micro-wire in the central area is electrically connected to the edge micro-wire in the edge area and is electrically isolated from the top-layer micro-wire; and wherein the

Assignees

Inventors

Classifications

  • H05K3/4685Primary

    Manufacturing of cross-over conductors · CPC title

  • Male die used for patterning, punching or transferring · CPC title

  • by using a substrate provided with a shape pattern, e.g. grooves, banks, resist pattern · CPC title

  • by other printing techniques, e.g. letterpress printing, intaglio printing, lithographic printing, offset printing · CPC title

  • Layout details of a single conductor · CPC title

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What does patent US9277642B2 cover?
A method of making an imprinted micro-wire structure includes providing a substrate having an edge area and a central area separate from the edge area and providing first, second, and third different stamps. A curable bottom, connecting layer, and top layer are formed on the substrate. A bottom-layer micro-channel is imprinted in the bottom layer in the central area and the edge area, a connect…
Who is the assignee on this patent?
Eastman Kodak Co
What technology area does this patent fall under?
Primary CPC classification H05K3/4685. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).