Approach to minimization of strain loss in strained fin field effect transistors

Patent metadata

Field	Value
Publication number	US-9818875-B1
Application number	US-201615295546-A
Country	US
Kind code	B1
Filing date	Oct 17, 2016
Priority date	Oct 17, 2016
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A method of fabricating a vertical fin field effect transistor with a strained channel, including, forming a strained vertical fin on a substrate, forming a plurality of gate structures on the strained vertical fin, forming an interlevel dielectric on the strained vertical fin, forming a source/drain contact on the vertical fin adjacent to each of the plurality of gate structures, and selectively removing one or more of the source/drain contacts to form a trench adjacent to a gate structure.

First claim

What is claimed is:

1. A method of fabricating a vertical fin field effect transistor with a strained channel, comprising:
forming a strained vertical fin on a substrate;
forming a plurality of gate structures on the strained vertical fin;
forming an interlevel dielectric on the strained vertical fin;
forming a source/drain contact on the strained vertical fin adjacent to each of the plurality of gate structures;
selectively removing one or more of the source/drain contacts to form a trench adjacent to a gate structure;
removing a portion of the strained vertical fin exposed by forming the trench; and
removing a portion of the substrate after removing the exposed portions of the strained vertical fin.

2. The method of claim 1 , further comprising forming an insulating liner in each trench and a trench fill on the insulating liner.

3. The method of claim 2 , wherein the insulating liner is silicon nitride (SiN), a silicon oxynitride (SiON), a silicon carbonitride (SiCN), a silicon boronitride (SiBN), a silicon borocarbide (SiBC), a silicon boro carbonitride (SiBCN), a boron carbide (BC), a boron nitride (BN), or combinations thereof.

4. The method of claim 1 , wherein the strained vertical fin is single crystal silicon-germanium (Site) and the substrate is single crystal silicon.

5. The method of claim 4 , further comprising forming a plurality of gate spacers on the strained vertical fin, wherein each of the plurality of gate structures is formed within one of the gate spacers.

6. The method of claim 1 , wherein the source/drain contacts are tungsten, titanium, cobalt, or a combination thereof.

7. The method of claim 6 , wherein the source/drain contacts are removed using a selective dry etch.

8. The method of claim 1 , wherein each trench is self-aligned with the adjacent gate structure after removal of the source/drain contacts by exposing a sidewall of the gate spacer between the trench and the adjacent gate structure.

9. A method of fabricating a vertical fin field effect transistor with a strained channel, comprising:
forming a strained silicon-germanium (SiGe) vertical fin on a single crystal silicon substrate or a strained silicon (Si) vertical fin on a single crystal silicon-germanium substrate;
forming three or more gate structures on the strained SiGe vertical fin or strained Si vertical fin;
forming a gate spacer on each of the three or more gate structures;
forming an interlevel dielectric on the gate spacers;
forming four or more openings in the interlevel dielectric;
forming four or more source/drain contacts in the interlevel dielectric on the strained SiGe vertical fin or strained Si vertical fin, where at least two of the source/drain contacts are between the gate spacers;
selectively removing one or more of the source/drain contacts to form a trench in the interlevel dielectric;
removing a portion of the strained SiGe vertical fin or strained Si vertical fin exposed by forming the trench; and
removing a portion of the substrate after removing the exposed portions of the strained SiGe vertical fin or strained Si vertical fin.

10. The method of claim 9 , wherein the strained silicon-germanium (SiGe) vertical fin is epitaxially grown on the single crystal silicon substrate, or the strained silicon (Si) vertical fin is epitaxially grown on a single crystal silicon-germanium substrate.

11. The method of claim 9 , wherein the height of the strained SiGe vertical fin and the germanium (Ge) concentration of the strained SiGe vertical fin are below a threshold value at which dislocations would appear in the vertical fin.

12. The method of claim 9 , wherein removing an exposed portion of the strained SiGe vertical fin or strained Si vertical fin from the one or more trenches forms a plurality of strained SiGe vertical fin sections or strained Si vertical fin sections.

13. The method of claim 12 , further comprising extending the one or more trenches into the substrate by a predetermined depth below the strained SiGe vertical fin or strained Si vertical fin.

14. The method of claim 13 , further comprising forming an insulating liner in each of the one or more trenches.

Assignees

• IBM

Inventors

• Bi Zhenxing
• Cheng Kangguo
• Li Juntao
• Xu Peng

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H01L29/785 Primary

  Electricity · mapped topic

• H01L29/1054

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L29/41791

  Electricity · mapped topic