Semiconductor device having embedded strain-inducing pattern

US9240481B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9240481-B2
Application numberUS-201514596291-A
CountryUS
Kind codeB2
Filing dateJan 14, 2015
Priority dateJun 25, 2012
Publication dateJan 19, 2016
Grant dateJan 19, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device, comprising: a pair of strain-inducing patterns formed in a substrate; an active region formed between the pair of strain-inducing patterns, and having an upper surface, a first side surface, and a second side surface opposite the first side surface; and a gate electrode crossing the active region, wherein each of interfaces between the active region and the pair of strain-inducing patterns has {111} surface formed by a directional etching process, and wherein each of the first and second side surfaces has {211} surface, the upper surface has {110} surface, and each of the interfaces is perpendicular to the upper surface. 2. The semiconductor device of claim 1 , wherein each of the interfaces is perpendicular to the first side surface and the second side surface.

Assignees

Inventors

Classifications

  • Structure · CPC title

  • Silicon, silicon germanium or germanium · CPC title

  • characterised by treatments done before the formation of the materials · CPC title

  • using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

  • of fin field-effect transistors [FinFET] · CPC title

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What does patent US9240481B2 cover?
A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, …
Who is the assignee on this patent?
Maeda Shigenobu, Fukutome Hidenobu, Ko Young-Gun, and 2 more
What technology area does this patent fall under?
Primary CPC classification H10D62/405. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 19 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).