Method to form strained channel in thin box SOI structures by elastic strain relaxation of the substrate

Patent metadata

Field	Value
Publication number	US-9236474-B2
Application number	US-201414186342-A
Country	US
Kind code	B2
Filing date	Feb 21, 2014
Priority date	Feb 21, 2014
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer.

First claim

What is claimed is:

1. A strained-channel FET comprising:
a source region;
a drain region;
a channel region;
a strain-inducing layer of a first semiconductor material adjacent the channel region and extending laterally across an area that includes the source, channel, and drain regions; and
at least one stress-relief trench formed in the strain-inducing layer such that a region of the strain-inducing layer at which stress is relieved by the at least one stress-relief trench imparts strain to the channel region, wherein the at least one stress-relief trench comprises a first plurality of trenches extending in a first direction and a second plurality of trenches extending in a second direction that is different from the first direction.

2. The strained-channel FET of claim 1 , wherein the source, drain, and channel regions are formed in an ultrathin semiconductor layer disposed on an ultrathin buried oxide layer.

3. The strained-channel FET of claim 2 , wherein the strain-inducing layer comprises SiGe or SiC and the source, drain, and channel regions are formed in Si.

4. The strained-channel FET of claim 3 , wherein the thickness of the strain-inducing layer is between 10 nm and 100 nm and the thickness of the ultrathin semiconductor layer is between 1 nm and 25 nm.

5. The strained-channel FET of claim 1 , wherein the first semiconductor material comprises an epitaxial layer formed on a substrate having a second semiconductor material that is chemically different from the first semiconductor material.

6. The strained-channel FET of claim 5 , wherein the first semiconductor material has a first lattice constant that differs from a second lattice constant in the second semiconductor material, wherein the difference in first and second lattice constants determine a stress in the strain-inducing layer prior to formation of the at least one stress-relief trench.

7. The strained-channel FET of claim 5 , wherein the first semiconductor material is SiGe or SiC and the second semiconductor material is Si.

8. The strained-channel FET of claim 1 , wherein the first plurality of trenches extends in a first lateral direction and the second plurality of trenches extends in a second lateral direction that is different from the first lateral direction.

9. The strained-channel FET of claim 8 , wherein the first plurality of trenches and the second plurality of trenches are filled with an electrical insulator.

10. The strained-channel FET of claim 9 , wherein the electrical insulator exhibits compressive or tensile stress.

11. The strained-channel FET of claim 8 , wherein the first plurality of trenches further extend through the strain-inducing layer and the second plurality of trenches do not extend through the strain-inducing layer.

Assignees

• St Microelectronics Inc

Inventors

• Morin Pierre

Classifications

• H10D86/215

  comprising FinFETs · CPC title

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H10D86/011

  comprising FinFETs · CPC title

• H10D86/01

  Manufacture or treatment · CPC title

• H10D84/853

  comprising FinFETs · CPC title