CMOS compatible thermopile with low impedance contact

Patent metadata

Field	Value
Publication number	US-9818795-B2
Application number	US-201615255243-A
Country	US
Kind code	B2
Filing date	Sep 2, 2016
Priority date	May 30, 2014
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

In described examples, an integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming active areas which provide transistor active areas for an NMOS transistor and a PMOS transistor of the CMOS transistors and provide n-type thermoelectric elements and p-type thermoelectric elements of the embedded thermoelectric device. Stretch contacts with lateral aspect ratios greater than 4:1 are formed over the n-type thermoelectric elements and p-type thermoelectric elements to provide electrical and thermal connections through metal interconnects to a thermal node of the embedded thermoelectric device. The stretch contacts are formed by forming contact trenches in a dielectric layer, filling the contact trenches with contact metal and subsequently removing the contact metal from over the dielectric layer. The stretch contacts are formed concurrently with contacts to the NMOS and PMOS transistors.

First claim

What is claimed is:

1. A method of forming an integrated circuit, the method comprising:
providing a substrate comprising silicon-based semiconductor material having a top surface;
forming isolation trenches in the substrate between active areas of the integrated circuit to laterally isolate active areas for an NMOS transistor and a PMOS transistor in an area for CMOS transistors of the integrated circuit, and for n-type thermoelectric elements and p-type thermoelectric elements of an embedded thermoelectric device of the integrated circuit, the n-type thermoelectric elements and the p-type thermoelectric elements being less than 300 nanometers wide at a narrowest position;
forming dielectric material in the isolation trenches to provide field oxide of the integrated circuit;
forming source and drain regions of the NMOS transistor and the PMOS transistor in the substrate adjacent to gate structures of the NMOS transistor and the PMOS transistor;
forming a pre-metal dielectric (PMD) layer over the substrate;
forming contact holes and contact trenches in the PMD layer, the contact holes having lateral aspect ratios of 1:1 to 1.5:1 at the top surface of the substrate and exposing the source and drain regions, and the contact trenches having lateral aspect ratios of greater than 4:1 at the top surface of the substrate and exposing the n-type thermoelectric elements and the p-type thermoelectric elements;
forming contact metal over the PMD layer so as to extend into the contact holes and the contact trenches and make electrical connections to the source and drain regions and the n-type thermoelectric elements and the p-type thermoelectric elements;
removing the contact metal from over a top surface of the PMD layer, leaving the contact metal in the contact holes to provide contacts to the source and drain regions and leaving the contact metal in the contact trenches to provide stretch contacts to the n-type thermoelectric elements and the p-type thermoelectric elements, the contacts having lateral aspect ratios of 1:1 to 1.5:1; and the stretch contacts having lateral aspect ratios greater than 4:1; and
forming a plurality of interconnects of metal levels and a plurality of vias of via levels of the integrated circuit connecting the stretch contacts to a thermal node.

2. The method of claim 1 , wherein forming the contact metal comprises forming a liner comprising titanium and forming a fill metal comprising tungsten on the liner.

3. The method of claim 1 , wherein forming the contact metal comprises forming a first liner of titanium, forming a second liner of titanium nitride on the first liner, and forming a fill metal comprising tungsten on the second liner.

4. The method of claim 1 , wherein forming the contact holes and the contact trenches is performed so that a width of the contact trenches is substantially equal to a width of the contact holes, and is less than a width of the n-type thermoelectric elements and the p-type thermoelectric elements at the top surface of the substrate.

5. The method of claim 1 , wherein forming the contact holes and the contact trenches is performed so that a width of the contact trenches is greater than a width of the contact holes, and is substantially equal to a width of the n-type thermoelectric elements and the p-type thermoelectric elements at the top surface of the substrate.

6. The method of claim 1 , wherein forming the contact holes and the contact trenches is performed so that a width of the contact trenches is greater than a width of the contact holes, and is greater than a width of the n-type thermoelectric elements and the p-type thermoelectric elements at the top surface of the substrate.

7. The method of claim 1 , wherein forming the isolation trenches is performed so that the n-type thermoelectric elements and the p-type thermoelectric elements are configured in arrays of linear active areas.

8. The method of claim 1 , wherein forming the isolation trenches is performed so that the n-type thermoelectric elements and the p-type thermoelectric elements are configured in rectangular arrays of pillar active areas.

9. The method of claim 1 , wherein forming the plurality of the interconnects includes forming interconnects of a first metal level on the stretch contacts, to make electrical and thermal connections to the stretch contacts, so as to overlap the stretch contacts by an overlap distance which is 25 percent to 50 percent of an average pitch of the stretch contacts.

10. The method of claim 1 , wherein forming the plurality of the vias includes forming stretch vias of a first via level on interconnects of a first metal level on the stretch contacts, the stretch vias of the first via level having lateral aspect ratios of greater than 4:1.

Assignees

• Texas Instruments Inc

Inventors

• Debord Jeffrey R
• Edwards Henry Litzmann
• Maggio Kenneth J

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/036

  the barrier, adhesion or liner layers being within a main fill metal · CPC title