Interconnect reliability structures

US9817063B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9817063-B2
Application numberUS-201615048704-A
CountryUS
Kind codeB2
Filing dateFeb 19, 2016
Priority dateFeb 19, 2016
Publication dateNov 14, 2017
Grant dateNov 14, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure relates to semiconductor structures and, more particularly, to interconnect reliability structures and methods of manufacture. The structure includes: a plurality of resistors; and a voltmeter configured to sense a relative difference in resistance of the plurality of resistors indicative of at least one of a via-depletion and line-depletion.

First claim

Opening claim text (preview).

What is claimed: 1. A structure, comprising: a plurality of resistors; and a voltmeter configured to sense a relative difference in resistance of the plurality of resistors indicative of at least one of a via-depletion and line-depletion, wherein each of the plurality of resistors comprise via chain structures which comprise: a single via interconnect on one side of a wiring layer of a dual damascene structure, and a plurality of via interconnects on another side of the wiring layer, and each of the plurality of via interconnects are in direct contact with each other and an upper wiring layer. 2. The structure of claim 1 , wherein the plurality of resistors comprise a first set of resistors having a first polarity and a second set of resistors having a second polarity. 3. The structure of claim 2 , wherein the first set of resistors and the second set of resistors form a Wheatstone bridge. 4. The structure of claim 2 , wherein the first set of resistors is configured to sense via depletion caused by electromigration and the second set of resistors is configured to sense line depletion caused by electromigration. 5. The structure of claim 4 , wherein: the plurality of resistors each comprise the dual damascene structure and an interconnect via structure in direct electrical connection with the wiring layer of the dual damascene structure; a liner material between the wiring layer of the dual damascene structure and the interconnect via structure; and a junction of the wiring layer and a via interconnect structure of the dual damascene structure is devoid of the liner material. 6. The structure of claim 5 , wherein the second set of resistors are on opposing sides of the voltmeter and are located such that electrons flow from the interconnect via structure into the dual damascene structure. 7. The structure of claim 5 , wherein the first set of resistors are on opposing sides of the voltmeter and are located such that electrons flow from the dual damascene structure into the interconnect via structure. 8. The structure of claim 1 , wherein the plurality of via interconnects on the other side of the wiring layer has a lower resistance than the single via interconnect. 9. The structure of claim 1 , wherein the plurality of resistors are connected to a wiring structure which has a line width greater than a line width of each of the resistors. 10. The structure of claim 1 , wherein the via chain structures further comprise an interconnect reliability structure. 11. The structure of claim 10 , wherein a liner is provided at a junction of a lower wiring layer and the single via interconnect and at a junction of the lower wiring layer and the plurality of via interconnects. 12. A structure, comprising: a first set of resistors having a first polarity; a second set of resistors having a second polarity; and a voltmeter configured to sense a relative difference in resistance between the first set of resistors and the second set of resistors, wherein each resistor of the first set of resistors and the second set of resistors comprise via chain structures which comprise: a single via interconnect on one side of a wiring layer of a dual damascene structure, and a plurality of via interconnects on another side of the wiring layer, and each of the plurality of via interconnects are in direct contact with each other and an upper wiring layer. 13. The structure of claim 12 , wherein the first set of resistors and the second set of resistors form a Wheatstone bridge. 14. The structure of claim 13 , wherein the first set of resistors comprise a via depletion electromigration structure and the second set of resistors comprise a line depletion electromigration structure. 15. The structure of claim 14 , wherein the second set of resistors are on opposing sides of the voltmeter and are located such that electrons flow from an interconnect via structure into the dual damascene structure. 16. The structure of claim 14 , wherein the first set of resistors are on opposing sides of the voltmeter and are located such that electrons flow from the dual damascene structure into an interconnect via structure. 17. The structure of claim 12 , wherein plurality of via interconnects on the other side of the wiring layer has a lower resistance than the single via interconnect. 18. The structure of claim 12 , wherein the plurality of resistors are connected to a wiring structure which has a line width greater than a line width of each of the resistors. 19. A method, comprising: continuously monitoring a voltage V WB during in-line current ramp based on a resistive difference between a first resistor and a second resistor in a Wheatstone bridge; determining a statistically significant shift direction of V WB shift in real time during the in-line current ramp; an increase of the shift direction in V WB is indicative of a line depletion failure; and a decrease of the shift direction in V WB is indicative of a via depletion failure. 20. The method of claim 19 , wherein: no statistically significant shift direction in V WB is indicative of no electromigration defects being found.

Assignees

Inventors

Classifications

  • Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

  • Vias, e.g. via plugs · CPC title

  • Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

  • Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection · CPC title

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US9817063B2 cover?
The present disclosure relates to semiconductor structures and, more particularly, to interconnect reliability structures and methods of manufacture. The structure includes: a plurality of resistors; and a voltmeter configured to sense a relative difference in resistance of the plurality of resistors indicative of at least one of a via-depletion and line-depletion.
Who is the assignee on this patent?
Globalfoundries Inc
What technology area does this patent fall under?
Primary CPC classification G01R31/2858. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 14 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).