Degradation detector and method of detecting the aging of an integrated circuit

Patent metadata

Field	Value
Publication number	US-9494641-B2
Application number	US-201414163066-A
Country	US
Kind code	B2
Filing date	Jan 24, 2014
Priority date	Jan 24, 2014
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

A degradation detector for an integrated circuit (IC), a method of detecting aging in an IC and an IC incorporating the degradation detector or the method. In one embodiment, the degradation detector includes: (1) an offline ring oscillator (RO) coupled to a power gate and a clock gate, (2) a frozen RO coupled to a clock gate, (3) an online RO and (4) an analyzer coupled to the offline RO, the frozen RO and the online RO and operable to place the degradation detector in a normal state in which the offline RO is disconnected from both the drive voltage source and the clock source, the frozen RO is connected to the drive voltage source but disconnected from the clock source and the online RO is connected to both the drive voltage source and the clock source.

First claim

What is claimed is:

1. A degradation detector for an integrated circuit, comprising:
an offline ring oscillator coupled to a drive voltage source via a power gate and a clock source via a first clock gate;
a frozen ring oscillator coupled to a second clock gate;
an online ring oscillator persistently coupled to said drive voltage source and said clock source; and
an analyzer coupled to said offline ring oscillator, said frozen ring oscillator and said online ring oscillator and operable to place said degradation detector in a normal state in which said offline ring oscillator is disconnected from both said drive voltage source and said clock source, said frozen ring oscillator is connected to said drive voltage source but disconnected from said clock source and said online ring oscillator is connected to both said drive voltage source and said clock source.

2. The degradation detector as recited in claim 1 wherein said degradation detector is associated with other integrated circuitry, inverters in said offline ring oscillator, said frozen ring oscillator and said online ring oscillator being of a same architecture as said other integrated circuitry.

3. The degradation detector as recited in claim 1 wherein said analyzer is further operable to place said degradation detector in a detection state in which said offline ring oscillator, said frozen ring oscillator and said online ring oscillator are connected to both said drive voltage source and said clock source.

4. The degradation detector as recited in claim 1 further comprising counters coupled to said offline ring oscillator, said frozen ring oscillator and said online ring oscillator and operable to provide numbers to said analyzer.

5. The degradation detector as recited in claim 1 further comprising duty cycle detectors coupled to said offline ring oscillator, said frozen ring oscillator and said online ring oscillator and operable to provide numbers to said analyzer.

6. The degradation detector as recited in claim 1 wherein said frozen ring oscillator is biased to provide maximum positive BTI stress and said degradation detector further comprises another frozen ring oscillator biased to provide maximum negative BTI stress.

7. The degradation detector as recited in claim 1 wherein said analyzer is further operable to provide a signal indicating an aging of said integrated circuit.

8. A method of detecting aging in an integrated circuit, comprising:
entering a normal state, including:
providing neither a drive voltage nor a clock signal to an offline ring oscillator,
providing said drive voltage but not said clock signal to a frozen ring oscillator, and
providing both said drive voltage and said clock signal to an online ring oscillator; and

entering a detection state from said normal state, said detection state including:
providing both said drive voltage and said clock signal to said offline ring oscillator,
providing both said drive voltage and said clock signal to said frozen ring oscillator, and
providing both said drive voltage and said clock signal to said online ring oscillator.

9. The method as recited in claim 8 wherein said offline ring oscillator, said frozen ring oscillator and said online ring oscillator are associated with other integrated circuitry, inverters in said offline ring oscillator, said frozen ring oscillator and said online ring oscillator being of a same architecture as said other integrated circuitry.

10. The method as recited in claim 8 further comprising providing numbers from counters coupled to said offline ring oscillator, said frozen ring oscillator and said online ring oscillator in said detection state.

11. The method as recited in claim 8 further comprising providing numbers from duty cycle detectors coupled to said offline ring oscillator, said frozen ring oscillator and said online ring oscillator in said detection state.

12. The method as recited in claim 8 wherein said frozen ring oscillator is biased to provide maximum positive BTI stress and said degradation detector further comprises another frozen ring oscillator biased to provide maximum negative BTI stress.

13. The method as recited in claim 8 further comprising providing a signal indicating an aging of said integrated circuit.

14. An integrated circuit, comprising:
memory;
other integrated circuitry; and
first and second power domains encompassing said memory and said other integrated circuitry, said memory being associated with a first degradation detector and said other integrated circuitry being associated with a second degradation detector, each said degradation detector including:
an offline ring oscillator coupled to a drive voltage source via a power gate and a clock source via a first clock gate,
a frozen ring oscillator coupled to a second clock gate,
an online ring oscillator oscillator persistently coupled to said drive voltage source and said clock source, and
an analyzer coupled to said offline ring oscillator, said frozen ring oscillator and said online ring oscillator and operable to place said degradation detector in a normal state in which said offline ring oscillator is disconnected from both said drive voltage source and said clock source, said frozen ring oscillator is connected to said drive voltage source but disconnected from said clock source and said online ring oscillator is connected to both said drive voltage source and said clock source, inverters in said offline ring oscillator, said frozen ring oscillator and said online ring oscillator of said first degradation detector being of a same architecture as said memory, inverters in said offline ring oscillator, said frozen ring oscillator and said online ring oscillator of said second degradation detector being of a same architecture as said other integrated circuitry.

15. The integrated circuit as recited in claim 14 further comprising first and second clock domains.

16. The integrated circuit as recited in claim 14 wherein said analyzer is further operable to place said degradation detector in a detection state in which said offline ring oscillator, said frozen ring oscillator and said online ring oscillator are connected to both said drive voltage source and said clock source.

17. The integrated circuit as recited in claim 14 wherein said degradation detector further comprising counters coupled to said offline ring oscillator, said frozen ring oscillator and said online ring oscillator and operable to provide numbers to said analyzer.

18. The integrated circuit as recited in claim 14 wherein said degradation detector further comprising duty cycle detectors coupled to said offline ring oscillator, said frozen ring oscillator and said online ring oscillator and operable to provide numbers to said analyzer.

19. The integrated circuit as recited in claim 14 wherein said frozen ring oscillator is biased to provide maximum positive BTI stress and said degradation detector further comprises another frozen ring oscillator biased to provide maximum negative BTI stress.

20. The integrated circuit as recited in claim 14 wherein said analyzer is further operable to provide a signal indicating an aging of said integrated circuit.

Assignees

• Nvidia Corp

Inventors

• Smith Brian
• Felix Stephen
• Raja Tezaswi
• Surgutchik Roman

Classifications

• H03K3/0315

  Ring oscillators · CPC title

• G01R31/2851

  Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801) · CPC title

• G01R1/30

  Structural combination of electric measuring instruments with basic electronic circuits, e.g. with amplifier · CPC title

• G01R31/2837

  Characterising or performance testing, e.g. of frequency response (transient response G01R27/28) · CPC title

• G01R31/31727

  Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922) · CPC title