Non-volatile memory device containing oxygen-scavenging material portions and method of making thereof

Patent metadata

Field	Value
Publication number	US-9812505-B2
Application number	US-201615157945-A
Country	US
Kind code	B2
Filing date	May 18, 2016
Priority date	Nov 16, 2015
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

A middle electrode can be inserted at each intersection between a non-volatile memory element layer located on an electrically conductive word line and a non-linear element located on an electrically conductive bit line in a three-dimensional memory device. An oxygen-scavenging material portion can be provided between each electrically conductive word line and an adjoining insulator layer to scavenge oxygen from contacting portions of the non-volatile memory element layer, thereby forming an oxygen-scavenged non-volatile memory element portion that facilitates programming. The middle electrode and the oxygen-scavenged non-linear memory element portion can alter the programming characteristics of the non-volatile memory cells to provide easier and more reliable programming.

First claim

What is claimed is:

1. A monolithic three-dimensional memory device, comprising:
a repeating stack of instances of a repetition unit comprising an insulating layer, a oxygen-scavenging material portion, and an electrically conductive word line, wherein the repeating stack is located over a substrate, and the oxygen-scavenging material portion comprises a material having a greater affinity to oxygen than a material of the electrically conductive word line;
at least one non-volatile memory element layer including oxygen-scavenged non-volatile memory element portions and non-scavenged non-volatile memory element portions;
at least one bit line extending along a direction of repetition in the repeating stack; and
at least one non-linear element material layer located between the at least one bit line and the at least one non-volatile memory element layer.

2. The monolithic three-dimensional memory device of claim 1 , further comprising middle electrodes located between the at least one non-linear element material layer and the at least one non-volatile memory element layer at same levels as the insulating layers, and contacting a respective oxygen-scavenged non-volatile memory element portion.

3. The monolithic three-dimensional memory device of claim 2 , wherein:
a material composition of the oxygen-scavenged non-volatile memory element portions differs from a composition of the non-scavenged non-volatile memory element portions by a lower atomic oxygen concentration;
sidewalls of the insulating layers are recessed with respect to sidewalls of the oxygen-scavenging material portions; and
each middle electrode contacts a sidewall and a bottom surface of a respective oxygen-scavenged non-volatile memory element portion.

4. The monolithic three-dimensional memory device of claim 3 , wherein each of the middle electrodes contacts a bottom surface of an overlying non-scavenged non-volatile memory element portion and a top surface of an underlying non-scavenged non-volatile memory element portion.

5. The monolithic three-dimensional memory device of claim 2 , wherein the oxygen-scavenged non-volatile memory material portions do not physically contact the at least one non-linear element material layer, but are laterally spaced from the at least one non-linear element material layer by a respective middle electrode.

6. The monolithic three-dimensional memory device of claim 1 , wherein the at least one non-linear element material layer comprises a continuous non-linear element material layer that contacts the middle electrodes and extends along the direction of repetition in the repeating stack.

7. The monolithic three-dimensional memory device of claim 1 , wherein the at least one non-linear element material layer comprises:
a plurality of discrete non-linear element material layers, wherein each of the plurality of discrete non-linear element material layers contacts only one of the middle electrodes; or
an assembly of a semiconductor channel layer and a gate dielectric layer, for which the at least one bit line functions as a gate electrode.

8. The monolithic three-dimensional memory device of claim 1 , wherein the repetition unit of the repeating stack further comprises a dielectric blocking material portion that retards diffusion of metallic elements and contacting a respective insulating layer and an element selected from an overlying oxygen-scavenging material portion and an underlying electrically conductive word line.

9. The monolithic three-dimensional memory device of claim 1 , wherein the middle electrodes have laterally protruding surfaces that protrude away from a respective insulating layer located at a same level.

10. The monolithic three-dimensional memory device of claim 1 , wherein the at least one bit line is at least one electrically conductive bit line including a conductive material.

Assignees

• Sandisk Technologies Llc

Inventors

• Sakotsubo Yukihiro

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H01L45/1233

  Electricity · mapped topic

• H01L45/08

  Electricity · mapped topic

• H01L27/2481 Primary

  Electricity · mapped topic

• H01L27/2436

  Electricity · mapped topic