Reducing disturb with adjustable resistance bit line structures

Patent metadata

Field	Value
Publication number	US-2016019957-A1
Application number	US-201514715586-A
Country	US
Kind code	A1
Filing date	May 18, 2015
Priority date	May 20, 2014
Publication date	Jan 21, 2016
Grant date	—

Abstract

Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.

First claim

What is claimed is:

1 . A method for operating a non-volatile memory, comprising:
identifying a first word line within a memory array; identifying a first global bit line within the memory array, the first global bit line is connected to an adjustable resistance bit line structure that includes an adjustable resistance local bit line and a select gate, a first memory cell is arranged between the adjustable resistance local bit line and the first word line; determining a plurality of unselected word line voltages to be applied to a plurality of unselected word lines within the memory array, a plurality of unselected memory cells is arranged between the adjustable resistance local bit line and the plurality of unselected word lines; and performing a memory operation on the memory array, the memory operation includes applying a selected word line voltage to the first word line and applying a selected bit line voltage to the first global bit line while the adjustable resistance local bit line is set into a conducting state, the memory operation includes applying the plurality of unselected word line voltages to the plurality of unselected word lines while the adjustable resistance local bit line is set into the conducting state.

2 . The method of claim 1 , wherein:
the memory operation comprises a RESET operation; and the determining a plurality of unselected word line voltages includes determining the plurality of unselected word line voltages such that the voltage stress across each of the plurality of unselected memory cells is substantially 0V prior to the first memory cell being RESET.

3 . The method of claim 1 , wherein:
the memory operation comprises a RESET operation; and the determining a plurality of unselected word line voltages includes determining the plurality of unselected word line voltages such that the voltage stress across each of the plurality of unselected memory cells is at most a particular voltage prior to the first memory cell being RESET.

4 . The method of claim 3 , wherein:
the particular voltage comprises 500 mV.

5 . The method of claim 1 , wherein:
the memory operation comprises a SET operation; and the determining a plurality of unselected word line voltages includes determining the plurality of unselected word line voltages such that the voltage stress across each of the plurality of unselected memory cells is substantially 0V after the first memory cell is SET.

6 . The method of claim 1 , wherein:
the memory operation comprises a SET operation; and the determining a plurality of unselected word line voltages includes determining the plurality of unselected word line voltages such that the voltage stress across each of the plurality of unselected memory cells is at most a threshold voltage after the first memory cell is SET.

7 . The method of claim 1 , wherein:
the determining a plurality of unselected word line voltages includes determining the plurality of unselected word line voltages based on locations of the plurality of unselected memory cells along the adjustable resistance local bit line.

8 . The method of claim 1 , further comprising:
identifying a dummy word line within the memory array, the dummy word line comprises the word line closest to the first global bit line; and generating a dummy word line voltage greater than any of the plurality of unselected word line voltages, the dummy word line voltage is less than the selected bit line voltage, the memory operation includes applying the dummy word line voltage to the dummy word line while the adjustable resistance local bit line is set into the conducting state.

9 . The method of claim 8 , wherein:
the determining a plurality of unselected word line voltages includes determining the plurality of unselected word line voltages for unselected word lines positioned between the first word line and the dummy word line, the dummy word line is arranged within a word line layer that is closest to a substrate.

10 . The method of claim 1 , wherein:
the memory operation comprises one of a programming operation or a read operation; the adjustable resistance local bit line comprises undoped polysilicon; the first memory cell comprises a ReRAM memory cell; and the memory array comprises a three-dimensional memory array.

11 . A non-volatile storage system, comprising:
a memory array, the memory array includes a first adjustable resistance bit line structure, the first adjustable resistance bit line structure includes an adjustable resistance local bit line and a select gate; and one or more managing circuits in communication with the first adjustable resistance bit line structure, the one or more managing circuits identify a first word line within the memory array, a first memory cell is arranged between the adjustable resistance local bit line and the first word line, the one or more managing circuits identify a first global bit line within the memory array, the first global bit line is connected to the adjustable resistance local bit line, the one or more managing circuits determine a plurality of unselected word line voltages to be applied to a plurality of unselected word lines, a plurality of unselected memory cells is arranged between the adjustable resistance local bit line and the plurality of unselected word lines, the one or more managing circuits cause a selected word line voltage to be applied to the first word line and a selected bit line voltage to be applied to the first global bit line while the adjustable resistance local bit line is set into a conducting state, the one or more managing circuits cause the plurality of unselected word line voltages to be applied to the plurality of unselected word lines while the adjustable resistance local bit line is set into the conducting state.

12 . The non-volatile storage system of claim 11 , wherein:
the one or more managing circuits cause the plurality of unselected word line voltages to be applied to the plurality of unselected word lines while the adjustable resistance local bit line is set into the conducting state during a memory operation.

13 . The non-volatile storage system of claim 12 , wherein:
the memory operation comprises a programming operation.

14 . The non-volatile storage system of claim 12 , wherein:
the one or more managing circuits determine the plurality of unselected word line voltages such that the voltage stress across each of the plurality of unselected memory cells is substantially 0V during at least a portion of the memory operation.

15 . The non-volatile storage system of claim 12 , wherein:
the one or more managing circuits determine the plurality of unselected word line voltages such that the voltage stress across each of the plurality of unselected memory cells is at most a particular voltage during at least a portion of the memory operation.

16 . The non-volatile storage system of claim 15 , wherein:
the particular voltage comprises 1V.

17 . The non-volatile storage system of claim 11 , wherein:
the one or more managing circuits determine the plurality of unselected word line voltages based on locations of the plurality of unselected memory cells along the adjustable resistance local bit line.

18 . The non-volatile storage system of claim 11 , wherein:
the one or more managing circuits identify a dummy word line within the memory array, the dummy word line comprises the word line closest to the first global bit line, the one or more managing circuits cause a dummy word line voltage to be applied to the dummy word li

Assignees

• Sandisk 3D Llc

Inventors

• Ratnam Perumal
• Petti Christopher
• Yan Tianhong

Classifications

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• G11C13/0097

  Erasing, e.g. resetting, circuits or methods · CPC title

• G11C13/0033 Primary

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C13/0028

  Word-line or row circuits · CPC title

• H10B63/34

  of the vertical channel field-effect transistor type · CPC title