Setting channel voltages using a dummy word line

Patent metadata

Field	Value
Publication number	US-2016019953-A1
Application number	US-201514715579-A
Country	US
Kind code	A1
Filing date	May 18, 2015
Priority date	May 20, 2014
Publication date	Jan 21, 2016
Grant date	—

Abstract

Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.

First claim

What is claimed is:

1 . A method for operating a non-volatile memory, comprising:
determining a first word line within a memory array; determining a first global bit line within the memory array, the first global bit line is connected to an adjustable resistance bit line structure that includes an adjustable resistance local bit line and a select gate, a first memory cell is arranged between the adjustable resistance local bit line and the first word line; determining a dummy word line within the memory array, the dummy word line comprises the word line closest to the first global bit line; determining a dummy word line voltage; and performing a memory operation on the memory array, the memory operation includes applying a selected word line voltage to the first word line and applying a selected bit line voltage to the first global bit line while the adjustable resistance local bit line is set into a conducting state, the memory operation includes applying the dummy word line voltage to the dummy word line while the adjustable resistance local bit line is set into the conducting state.

2 . The method of claim 1 , further comprising:
determining an unselected word line voltage to be applied to a set of unselected word lines, a set of unselected memory cells is arranged between the adjustable resistance local bit line and the set of unselected word lines, the dummy word line voltage is greater than the unselected word line voltage, the memory operation includes applying the unselected word line voltage to the set of unselected word lines during the memory operation.

3 . The method of claim 1 , wherein:
the determining a dummy word line voltage includes determining the dummy word line voltage based on the memory operation, the dummy word line voltage is less than the selected bit line voltage, the dummy word line voltage is greater than the selected word line voltage.

4 . The method of claim 1 , wherein:
the selected word line voltage is less than the selected bit line voltage.

5 . The method of claim 1 , wherein:
the memory operation comprises a RESET operation.

6 . The method of claim 1 , wherein:
the memory operation comprises a read operation.

7 . The method of claim 1 , wherein:
the adjustable resistance local bit line comprises undoped polysilicon.

8 . The method of claim 1 , wherein:
the first memory cell comprises a ReRAM memory cell; and the memory array comprises a three-dimensional memory array.

9 . The method of claim 1 , further comprising:
determining a maximum current limit for the first memory cell; determining a selected select gate voltage based on the maximum current limit; and applying the selected select gate voltage to the select gate during the memory operation, the applying the dummy word line voltage to the dummy word line is performed prior to the applying the selected select gate voltage to the select gate.

10 . The method of claim 1 , further comprising:
determining a maximum current limit for the first memory cell, the memory operation includes applying a selected select gate voltage to the select gate such that a current through the first memory cell does not exceed the maximum current limit for the first memory cell.

11 . A non-volatile storage system, comprising:
a memory array, the memory array includes a first adjustable resistance bit line structure, the first adjustable resistance bit line structure includes an adjustable resistance local bit line and a select gate; and one or more managing circuits in communication with the first adjustable resistance bit line structure, the one or more managing circuits identify a first word line within the memory array, a first memory cell is arranged between the adjustable resistance local bit line and the first word line, the one or more managing circuits identify a first global bit line within the memory array, the first global bit line is connected to the adjustable resistance local bit line, the one or more managing circuits identify a dummy word line within the memory array, the dummy word line comprises the word line closest to the first global bit line, the one or more managing circuits determine a dummy word line voltage, the one or more managing circuits cause the adjustable resistance local bit line to be set into a conducting state during a memory operation, the one or more managing circuits cause a selected word line voltage to be applied to the first word line and a selected bit line voltage to be applied to the first global bit line while the adjustable resistance local bit line is set into the conducting state, the one or more managing circuits cause the dummy word line voltage to be applied to the dummy word line while the adjustable resistance local bit line is set into the conducting state.

12 . The non-volatile storage system of claim 11 , wherein:
the one or more managing circuits identify a set of unselected word lines, a set of unselected memory cells is arranged between the adjustable resistance local bit line and the set of unselected word lines, the one or more managing circuits determine an unselected word line voltage, the dummy word line voltage is greater than the unselected word line voltage, the one or more managing circuits cause the unselected word line voltage to be applied to at least one of the set of unselected word lines during the memory operation.

13 . The non-volatile storage system of claim 11 , wherein:
the selected word line voltage is less than the selected bit line voltage.

14 . The non-volatile storage system of claim 11 , wherein:
the dummy word line voltage is less than the selected bit line voltage, the dummy word line voltage is greater than the selected word line voltage.

15 . The non-volatile storage system of claim 11 , wherein:
the memory operation comprises one of a RESET operation or a SET operation.

16 . The non-volatile storage system of claim 11 , wherein:
the memory operation comprises a read operation.

17 . The non-volatile storage system of claim 11 , wherein:
the adjustable resistance local bit line comprises undoped polysilicon.

18 . The non-volatile storage system of claim 11 , wherein:
the first memory cell comprises a ReRAM memory cell; and the memory array comprises a three-dimensional memory array.

19 . A method for operating a non-volatile memory, comprising:
identifying a dummy word line within a memory array, the memory array includes a first word line and a first global bit line, the first global bit line is connected to an adjustable resistance bit line structure that includes an adjustable resistance local bit line and a select gate, a first memory cell is arranged between the adjustable resistance local bit line and the first word line, the dummy word line comprises the word line closest to the first global bit line; determining a dummy word line voltage; determining a maximum current limit for the first memory cell; determining a selected select gate voltage based on the maximum current limit; and performing a memory operation on the memory array, the memory operation includes applying a selected word line voltage to the first word line and applying a selected bit line voltage to the first global bit line while the adjustable resistance local bit line is set into a conducting state, the memory operation includes applying the dummy word line voltage to the dummy word line while the adjustable resistance local bit line is set into the conducting state, the memory operation includes applying the selected s

Assignees

• Sandisk 3D Llc

Inventors

• Ratnam Perumal
• Petti Christopher
• Yan Tianhong

Classifications

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C13/0097

  Erasing, e.g. resetting, circuits or methods · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title