Operation modes for adjustable resistance bit line structures

Patent metadata

Field	Value
Publication number	US-2016019960-A1
Application number	US-201514715575-A
Country	US
Kind code	A1
Filing date	May 18, 2015
Priority date	May 20, 2014
Publication date	Jan 21, 2016
Grant date	—

Abstract

Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.

First claim

What is claimed is:

1 . A method for operating a non-volatile memory, comprising:
identifying a first word line within a memory array; identifying a first global bit line within the memory array, the first global bit line is connected to an adjustable resistance bit line structure, the adjustable resistance bit line structure includes an adjustable resistance local bit line and a select gate, a first memory cell is arranged between the adjustable resistance local bit line and the first word line; setting the adjustable resistance local bit line into a conducting state by applying a first voltage to the select gate; and performing a memory operation on the memory array, the memory operation includes applying a selected word line voltage to the first word line and a selected bit line voltage to the first global bit line while the adjustable resistance local bit line is set into the conducting state.

2 . The method of claim 1 , wherein:
the memory operation comprises a programming operation.

3 . The method of claim 1 , wherein:
the adjustable resistance local bit line comprises undoped polysilicon.

4 . The method of claim 1 , wherein:
the first memory cell comprises a ReRAM memory cell; and the memory array comprises a three-dimensional memory array.

5 . The method of claim 1 , further comprising:
identifying a second global bit line within the memory array, the second global bit line is connected to a second adjustable resistance bit line structure, the second adjustable resistance bit line structure includes a second adjustable resistance local bit line and a second select gate, a second memory cell is arranged between the second adjustable resistance local bit line and the first word line; and setting the second adjustable resistance local bit line into a non-conducting state by applying a second voltage different from the first voltage to the second select gate, the memory operation includes applying the selected word line voltage to the first word line while the adjustable resistance local bit line is set into the conducting state and the second adjustable resistance local bit line is set into the non-conducting state.

6 . The method of claim 1 , further comprising:
identifying a second global bit line within the memory array, the second global bit line is connected to a second adjustable resistance bit line structure, the second adjustable resistance bit line structure includes a second adjustable resistance local bit line and a second select gate, a second memory cell is arranged between the second adjustable resistance local bit line and the first word line; and setting the second adjustable resistance local bit line into a conducting state by applying the first voltage to the second select gate, the memory operation includes applying an unselected bit line voltage to the second global bit line while the adjustable resistance local bit line is set into the conducting state and the second adjustable resistance local bit line is set into the conducting state.

7 . The method of claim 1 , wherein:
the applying a first voltage to the select gate includes enabling a vertical thin-film transistor arranged above the select gate to pass the first voltage to the select gate.

8 . A non-volatile storage system, comprising:
a memory array, the memory array includes a first intrinsic bit line and a second intrinsic bit line, the first intrinsic bit line connected to a first set of memory cells, the second intrinsic bit line connected a second set of memory cells; and one or more managing circuits in communication with the first intrinsic bit line and the second intrinsic bit line, the one or more managing circuits configured to set the first intrinsic bit line to a first resistance and the second intrinsic bit line to a second resistance less than the first resistance during a memory operation.

9 . The non-volatile storage system of claim 8 , wherein:
the first intrinsic bit line comprises a non-conductive bit line during the memory operation, the second intrinsic bit line comprises a conductive bit line during the memory operation.

10 . The non-volatile storage system of claim 8 , wherein:
the first intrinsic bit line comprises undoped polysilicon.

11 . The non-volatile storage system of claim 8 , wherein:
the first intrinsic bit line comprises a vertical intrinsic bit line that is arranged in a direction that is substantially orthogonal to a substrate.

12 . The non-volatile storage system of claim 8 , wherein:
the first set of memory cells includes ReRAM memory cells; the memory operation comprises a programming operation; and the memory array comprises a three-dimensional memory array.

13 . A non-volatile memory, comprising:
a memory array, the memory array includes a first adjustable resistance bit line structure and a second adjustable resistance bit line structure, the first adjustable resistance bit line structure connected to a first set of memory cells, the second adjustable resistance bit line structure connected a second set of memory cells; and one or more managing circuits in communication with the first adjustable resistance bit line structure and the second adjustable resistance bit line structure, the one or more managing circuits configured to set the first adjustable resistance bit line structure into a conducting state and the second adjustable resistance bit line structure into a non-conducting state during a memory operation.

14 . The non-volatile memory of claim 13 , wherein:
the first adjustable resistance bit line structure includes a select gate surrounded by a layer of gate oxide, the layer of gate oxide surrounded by a layer of undoped polysilicon, the layer of undoped polysilicon surrounded by a layer of ReRAM material.

15 . The non-volatile memory of claim 13 , wherein:
the first adjustable resistance bit line structure includes a first semiconducting body region and a first select gate, the first semiconducting body region separated from the first select gate by a gate dielectric, the first semiconducting body region includes undoped polysilicon.

16 . The non-volatile memory of claim 15 , wherein:
the one or more managing circuits configured to apply a first voltage to the first select gate during the memory operation, the application of the first voltage to the first select gate causes a carrier concentration in the first semiconducting body region to increase.

17 . The non-volatile memory of claim 13 , wherein:
the first set of memory cells includes a first set of ReRAM memory cells; the second set of memory cells includes a second set of ReRAM memory cells; and the memory array comprises a three-dimensional memory array.

18 . The non-volatile memory of claim 13 , wherein:
the memory operation comprises one of a read operation or a programming operation.

19 . The non-volatile memory of claim 13 , wherein:
the one or more managing circuits identify a first word line within the memory array and identify a first global bit line within the memory array, the first global bit line is connected to the first adjustable resistance bit line structure, the first adjustable resistance bit line structure includes an adjustable resistance local bit line and a select gate, a first memory cell is arranged between the adjustable resistance local bit line and the first word line, the one or more managing circuits set the adjustable resistance local bit line into the conducting state by applying a first voltage to the select gate.

Assignees

• Sandisk 3D Llc

Inventors

• Ratnam Perumal
• Petti Christopher
• Yan Tianhong

Classifications

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C2216/10

  Floating gate memory cells with a single polysilicon layer · CPC title