Three-dimensional semiconductor device

Patent metadata

Field	Value
Publication number	US-9812464-B1
Application number	US-201715437426-A
Country	US
Kind code	B1
Filing date	Feb 20, 2017
Priority date	May 17, 2016
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

A three-dimensional semiconductor device may include a lower electrode structure having a plurality of lower electrodes vertically stacked on a substrate and an upper electrode structure having a plurality of upper electrodes stacked on the lower electrode structure. Each of the lower and upper electrodes may include an electrode portion that is parallel to a top surface of the substrate and a vertical pad portion that is inclined with respect to the top surface of the substrate. The vertical pad portions of adjacent lower electrodes may be spaced apart from each other by a first horizontal distance. The vertical pad portions of adjacent lower and upper electrodes may be spaced apart from each other by a second horizontal distance that is greater than the first horizontal distance.

First claim

What is claimed is:

1. A three-dimensional semiconductor device, comprising:
a lower electrode structure including a plurality of lower electrodes that are vertically stacked on a substrate; and
an upper electrode structure including a plurality of upper electrodes that are stacked on the lower electrode structure,
wherein each of the lower and upper electrodes comprises an electrode portion that is substantially parallel to a top surface of the substrate and a vertical pad portion that is inclined with respect to the top surface of the substrate,
the vertical pad portions of adjacent lower electrodes are spaced apart from each other by a first horizontal distance, and
the vertical pad portions of adjacent lower and upper electrodes are spaced apart from each other by a second horizontal distance that is greater than the first horizontal distance.

2. The device of claim 1 , wherein the vertical pad portions of the lower and upper electrodes comprise top surfaces that are positioned at substantially a same level from the substrate.

3. The device of claim 1 , wherein, in an adjacent pair of the lower and upper electrodes, a vertical distance between the electrode portions is less than the second horizontal distance between the vertical pad portions.

4. The device of claim 1 , wherein the electrode portions of adjacent lower electrodes are spaced apart from each other by a first vertical distance that is substantially the same as the first horizontal distance.

5. The device of claim 1 , wherein the vertical pad portions of adjacent upper electrodes are spaced apart from each other by the first horizontal distance, and
the electrode portions of adjacent upper electrodes are spaced apart from each other by a first vertical distance that is substantially a same distance as the first horizontal distance.

6. The device of claim 1 , further comprising a mold pattern that is interposed between the vertical pad portions of the adjacent pair of the lower and upper electrodes.

7. The device of claim 6 , wherein a top surface of the mold pattern is positioned at substantially the same level as the top surfaces of the vertical pad portions of the lower and upper electrodes with respect to the top surface of the substrate.

8. The device of claim 1 , wherein the lower electrode structure further comprises lower insulating layers that are respectively provided between the lower electrodes,
wherein the upper electrode structure further comprises upper insulating layers that are respectively provided between the upper electrodes,
wherein the three-dimensional semiconductor device further comprises a buffer pattern that is provided between the vertical pad portions of the adjacent pair of the lower and upper electrodes, and the buffer pattern is formed from an insulating material that is different from a material forming the lower and upper insulating layers.

9. The device of claim 1 , further comprising:
first contact plugs respectively coupled to the vertical pad portions of the lower electrodes; and
second contact plugs respectively coupled to the vertical pad portions of the upper electrodes,
wherein the first contact plugs have substantially a same length as a length of the second contact plugs.

10. The device of claim 1 , wherein the lower and upper electrode structures extend in a first direction that is substantially parallel to the top surface of the substrate, and
a length, in the first direction, of the electrode portions of the lower and upper electrodes decreases with increasing distance from the substrate.

11. A semiconductor memory device, comprising:
a first layered electrode structure on a surface of a substrate, the first layered electrode structure comprising a plurality of first electrodes stacked in a first direction away from the substrate, each first electrode comprising a horizontal electrode portion and a vertical pad portion disposed at a first end of the horizontal portion, the horizontal electrode portion of a first electrode extending substantially in a second direction and the vertical pad portion of a first electrode extending substantially in the first direction, the second direction being substantially parallel to the surface of the substrate, the first ends of the horizontal portions and the corresponding vertical pad portions of the first electrodes being grouped together, and the vertical pad portions of the first electrodes being spaced apart from each other in the second direction by a first distance; and
a second layered electrode structure on the first layered electrode structure, the second layered electrode structure comprising a plurality of second electrodes stacked in the first direction away from the substrate, each second electrode comprising a horizontal electrode portion and a vertical pad portion disposed at a first end of the horizontal portion, the horizontal electrode portion of a second electrode extending substantially in the second direction and the vertical pad portion of a second electrode extending substantially in the first direction, the first ends of the horizontal portions and the vertical pad portions of the second electrodes being grouped together, the grouped-together vertical pad portions of the second electrodes being spaced apart in the second direction from the grouped-together vertical pad portions of the first electrodes by a second distance that is greater than the first distance.

12. The semiconductor device of claim 11 , wherein the first direction forms an angle with a top surface of the substrate that ranges from about 90 degrees to about 130 degrees with respect to the top surface of the substrate.

13. The semiconductor device of claim 11 , wherein the first direction is substantially perpendicular to the top surface of the substrate.

14. The semiconductor device of claim 11 , wherein the vertical pad portions of the first electrodes and the vertical pad portions of the second electrodes each comprise a top surface, and
wherein the top surfaces of the vertical pad portions of the first electrodes and the top surfaces of the second electrodes are at substantially a same level from the top surface of the substrate.

15. The semiconductor device of claim 11 , further comprising a plurality of vertical structures each extending substantially in a fourth direction through the horizontal portions of the plurality of first electrodes and the horizontal portions of the plurality of second electrodes, at least one vertical structure comprising a memory device structure, and the fourth direction being perpendicular to the top surface of the substrate.

16. The semiconductor device of claim 15 , wherein the memory device structure comprises a plurality of memory cells, each memory cell corresponding to one of the first electrodes or one of the second electrodes.

17. The semiconductor device of claim 16 , wherein the memory device structure comprises a NAND FLASH memory device.

18. The semiconductor device of claim 11 , wherein the plurality of first electrodes are further arranged into a plurality of stacks of first electrodes, each stack of first electrodes being separated from each other in a third direction, the third direction being substantially perpendicular to the second direction, and
wherein the plurality of second electrodes are further arranged into a plurality of stacks of second electrodes, each stack of first electrodes being separated from each other in the third direction and each stack of second electrodes corresponding to a stack of first electrodes.

19. The semicon

Assignees

• Hwang Sung-Min
• Samsung Electronics Co Ltd

Inventors

• Hwang Sung-Min

Classifications

• H01L23/528

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L23/5226

  Electricity · mapped topic

• H01L23/535

  Electricity · mapped topic

• H10B41/50

  characterised by the boundary region between the core region and the peripheral circuit region · CPC title