3-D IC device with enhanced contact area

Patent metadata

Field	Value
Publication number	US-9236346-B2
Application number	US-201514617420-A
Country	US
Kind code	B2
Filing date	Feb 9, 2015
Priority date	Mar 13, 2013
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

A device includes a substrate with a recess, having a bottom and sides, extending into the substrate from the substrate's upper surface. The sides include first and second sides oriented transversely to one another. A stack of alternating active and insulating layers overlie the substrate's surface and the recess. At least some of the active layers have an upper and lower portions extending along upper and lower planes over and generally parallel to the upper surface and to the bottom, respectively. The active layers have first and second upward extensions positioned along the first and second sides to extend from the lower portions of their respective active layers. Conductive strips adjoin the second upward extensions of the said active layers. The conductive strips can comprise sidewall spacers on the sides of the second upward extensions, the conductive strips connected to overlying conductors by interlayer conductors.

First claim

What is claimed is:

1. A device comprising:
a substrate comprising an upper surface and a recess extending into the substrate from the upper surface;
the recess having a bottom and sides extending between the upper surface and the bottom, the sides comprising first and second sides oriented transversely to one another;
a stack of alternating active and insulating layers overlying the recess;
each of a plurality of said active layers having a lower portion extending along a lower plane over and generally parallel to the bottom;
each of the plurality of said active layers comprising first and second upward extensions positioned along the first and second sides and extending from the lower portions of their respective active layers;
the second upward extensions having lengths with lower ends towards the bottom and upper ends; and
a plurality of conductive strips adjoining the second upward extensions of the plurality of said active layers along their lengths towards but not past their upper ends.

2. The device of claim 1 , wherein:
the stack of alternating active and insulating layers also overlies the upper surface of the substrate and the recess; and
each of the plurality of active layers also has an upper portion extending along in a plane over and generally parallel to the upper surface.

3. The device of claim 2 , wherein the first upward extensions connect the upper and lower portions of their respective active layers.

4. The device of claim 2 , wherein:
the upper surface comprises an array area adjacent to the recess; and
the stack of alternating active and insulating layers comprises elements of a memory array at the array area.

5. The device of claim 1 , wherein the second upward extensions are oriented generally perpendicular to the upper surface and the first upward extensions are downwardly and inwardly sloped at an acute angle to the upper surface.

6. The device of claim 1 , wherein:
the recess is a generally rectangular recess with a third side opposite the first side and a fourth side opposite the second side; and
the second and fourth sides are oriented generally perpendicular to the upper surface and the first and third side are downwardly and inwardly sloped oriented at acute angles to the upper surface.

7. The device of claim 1 , wherein the upper surface and the bottom are generally parallel to one another.

8. A device comprising:
a substrate comprising an upper surface and a recess extending into the substrate from the upper surface;
the recess having a bottom and sides extending between the upper surface and the bottom, the sides comprising first and second sides oriented transversely to one another;
a stack of alternating active and insulating layers overlying the recess;
each of a plurality of said active layers having a lower portion extending along a lower plane over and generally parallel to the bottom;
each of the plurality of said active layers comprising first and second upward extensions positioned along the first and second sides and extending from the lower portions of their respective active layers; and
a plurality of conductive strips adjoining the second upward extensions of the plurality of said active layers, the plurality of conductive strips comprising sidewall spacers on sides of the second upward extensions.

9. A device comprising:
a substrate comprising an upper surface and a recess extending into the substrate from the upper surface;
the recess having a bottom and sides extending between the upper surface and the bottom, the sides comprising first and second sides oriented transversely to one another;
a stack of alternating active and insulating layers overlying the recess;
each of a plurality of said active layers having a lower portion extending along a lower plane over and generally parallel to the bottom;
each of the plurality of said active layers comprising first and second upward extensions positioned along the first and second sides and extending from the lower portions of their respective active layers; and
a plurality of conductive strips adjoining the second upward extensions of the plurality of said active layers, the conductive strips having lower and upper ends, the lower ends being in the recess, the upper ends being configured to connect to overlying conductors by interlayer conductors.

10. The device of claim 9 , wherein the upper ends of at least some of the conductive strips are at the same level, the same level being parallel to the upper surface.

11. The device of claim 9 , wherein the upper ends are at different levels relative to the upper surface.

12. The device of claim 9 , wherein the upper ends of the conductive strips provide landing areas for the interlayer conductors.

13. The device of claim 9 , wherein the upper ends of the conductive strips and adjacent ones of the second upward extensions provide landing areas for the interlayer conductors.

14. A method for forming electrical connections with active layers of a stack of alternating active and insulating layers of a device, the method comprising:
forming a recess in a substrate, the substrate comprising an upper surface with the recess extending into the substrate from the upper surface, the recess having a bottom and sides extending between the upper surface and the bottom, the sides comprising first and second sides oriented transversely to one another;
forming a stack of alternating active and insulating layers over the recess;
the stack forming step comprising:
forming a lower portion of each of the plurality of active layers to be along a lower plane and over and generally parallel to the bottom; and
forming first and second upward extensions of each of the plurality of active layers to be positioned along the first and second sides and to extend from the lower portions of their respective active layers; and

during the stack forming step, forming conductive strips adjoining the second upward extensions of the plurality of active layers.

15. The method of claim 14 , wherein the stack forming step also forms: (a) the said stack of alternating active and insulating layers over the upper surface of the substrate; and (b) an upper portion of each of a plurality of the active layers to be along and a plane and over and generally parallel to the upper surface.

16. The method of claim 14 , wherein the recess forming step comprises forming the first side as a downwardly and inwardly sloped first side oriented at an acute angle to the upper surface.

17. The method of claim 16 , wherein:
the recess forming step comprises forming the second side oriented generally perpendicular to the upper surface;
the conductive strips forming step comprising depositing a layer of conductive material along the bottom and sides of the recess, and anisotropically etching the conductive material; and
selecting the acute angle of the sloped first side so that the conductive material is removed from along the bottom and the first side during the anisotropically etching of the conductive material while leaving conductive material along the second side thereby forming a conductive strip.

18. The method of claim 16 , wherein:
the recess forming step comprises forming a generally rectangular recess having first, second, third and fourth sides with the first and third sides being opposite one another and being downwardly and inwardly sloped sides oriented at acute angles to the upper surface; and
the conductive strips forming step comprises forming the conductive strips as sidewall spacers at the second and fourth sides

Assignees

• Macronix Int Co Ltd

Inventors

• Hu Chih-Wei
• Yeh Teng-Hao

Classifications

• H10W20/0636

  the conductive members being on sidewalls · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/031 Primary

  of conductive parts of the interconnections · CPC title

• H10W20/01

  Manufacture or treatment · CPC title