Bonding wire for semiconductor devices

Patent metadata

Field	Value
Publication number	US-9812421-B2
Application number	US-201415105707-A
Country	US
Kind code	B2
Filing date	Dec 4, 2014
Priority date	Dec 17, 2013
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

Provided is a bonding wire capable of reducing the occurrence of defective loops. The bonding wire includes: a core material which contains more than 50 mol % of a metal M; an intermediate layer which is formed over the surface of the core material and made of Ni, Pd, the metal M, and unavoidable impurities, and in which the concentration of the Ni is 15 to 80 mol %; and a coating layer formed over the intermediate layer and made of Ni, Pd and unavoidable impurities. The concentration of the Pd in the coating layer is 50 to 100 mol %. The metal M is Cu or Ag, and the concentration of Ni in the coating layer is lower than the concentration of Ni in the intermediate layer.

First claim

The invention claimed is:

1. A bonding wire for a semiconductor device comprising:
a core material containing more than 50 mol % of a metal M;
an intermediate layer formed over a surface of the core material and made of nickel (Ni), palladium (Pd), the metal M, and unavoidable impurities, concentration of the Ni being 15 to 80 mol %; and
a coating layer formed over the intermediate layer and made of Ni, Pd and unavoidable impurities, concentration of the Pd being 50 to 100 mol %,
wherein the metal M is copper (Cu) or silver (Ag), and the concentration of the Ni in the coating layer is lower than concentration of the Ni in the intermediate layer.

2. The bonding wire according to claim 1 , wherein a thickness of the intermediate layer is 8 to 80 nm.

3. The bonding wire according to claim 1 , wherein
the coating layer further contains gold (Au), and the bonding wire further comprises a surface layer formed over the coating layer and made of an alloy containing Au and Pd, concentration of the Au being 10 to 70 mol %, the sum total concentration of the Au and the Pd being 80 mol % or more,
wherein the concentration of the Au in the coating layer is lower than the concentration of the Au in the surface layer.

4. The bonding wire according to claim 3 , wherein a total thickness of the surface layer, the coating layer, and the intermediate layer is 25 to 200 nm.

5. The bonding wire according to claim 3 , wherein a thickness of the surface layer is 3 to 30 nm.

6. The bonding wire according to claim 1 , wherein: the metal M is Cu; the core material contains one or more elements selected from phosphorus (P), titanium (Ti), boron (B) and Ag; and a total concentration of the one or more elements contained in the bonding wire is in the range of 0.0005 to 0.02 mass %.

7. The bonding wire according to claim 1 , wherein: the metal M is Cu; the core material contains one or more elements selected from Pd and Ni; and a total concentration of the one or more elements contained in the bonding wire is in the range of 0.2 to 2.0 mass %.

8. The bonding wire according to claim 1 , wherein: the metal M is Ag; the core material contains one or more elements selected from Pd, Ni and Cu; and a total concentration of the one or more elements contained in the bonding wire is in the range of 0.5 to 5.0 mass %.

9. The bonding wire according to claim 1 , wherein the coating layer further contains the same metal M as that contained in the core material.

Assignees

• Nippon Steel & Sumikin Mat Co
• Nippon Micrometal Corp

Inventors

• Uno Tomohiro
• Hagiwara Yoshiaki
• Oyamada Tetsuya
• Oda Daizo

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/07553

  changes in shapes · CPC title

• H10W72/5525

  comprising copper [Cu] · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title