System and method for a switch having a normally-on transistor and a normally-off transistor

Patent metadata

Field	Value
Publication number	US-9793260-B2
Application number	US-201514822530-A
Country	US
Kind code	B2
Filing date	Aug 10, 2015
Priority date	Aug 10, 2015
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

In accordance with an embodiment, a method includes conducting a reverse current through a first switch that includes a normally-on transistor coupled in series with a normally-off transistor between a first switch node and a second switch node. While conducting the reverse current, the first switch is turned-off by turning-off the normally-off transistor via a control node of the normally-off transistor and reducing a drive voltage of the normally-on transistor by decreasing a voltage between the control node of the normally-on transistor and a reference node of the normally-on transistor. After turning-off the first switch, a second switch coupled to the first switch is turned on.

First claim

What is claimed is:

1. A method of operating a first switch coupled between a first switch node and a second switch node, the first switch comprising a normally-on transistor coupled in series with a normally-off transistor, the method comprising:
conducting a reverse current through the first switch, wherein the reverse current corresponds to a positive voltage between the second switch node and the first switch node, and the reverse current flows from a source node of the normally-on transistor to a drain node of the normally-on transistor;
turning-on the first switch comprising turning on the normally-on transistor via a control node of the normally-on transistor and turning-on the normally-off transistor via a control node of the normally-off transistor;
while conducting the reverse current, turning off the first switch comprising turning-off the normally-off transistor via the control node of the normally-off transistor and reducing a drive voltage of the normally-on transistor by decreasing a voltage between the control node of the normally-on transistor and a reference node of the normally-on transistor; and
turning on a second switch coupled between the first switch and a supply node after turning off the first switch.

2. The method of claim 1 , wherein the second switch is coupled between the second switch node and the supply node.

3. The method of claim 1 , wherein turning-off the normally-on transistor and reducing the drive voltage of the normally-on transistor are performed at substantially the same time.

4. The method of claim 1 , wherein:
the normally-on transistor comprises a gallium nitride (GaN) high electron mobility transistor (HEMT); and
the normally-off transistor comprises an enhancement mode MOSFET.

5. The method of claim 1 , wherein:
turning-off the normally-off transistor comprises driving the control node of the normally-off transistor from a first voltage to a second voltage using a first driving circuit; and
reducing the drive voltage of the normally-on transistor comprises driving the control node of the normally-on transistor with a capacitor having a first terminal coupled to the control node of the normally-off transistor and a second terminal coupled to the control node of the normally-on transistor.

6. The method of claim 5 , wherein:
turning on the normally-off transistor via the control node of the normally-off transistor comprises driving the control node of the normally-off transistor from the second voltage to the first voltage; and
turning on the normally-on transistor via a control node of the normally-on transistor comprises driving the control node of the normally-on transistor using a clamp circuit coupled between the control node of the normally-on transistor and a source node of the normally-off transistor.

7. The method of claim 6 , wherein the clamp circuit comprises a diode coupled between the control node of the normally-on transistor and the source node of the normally-off transistor.

8. The method of claim 1 , wherein turning-on the first switch, turning-off the normally-off transistor and reducing the drive voltage of the normally-on transistor is performed in response to a switching signal.

9. The method of claim 1 , wherein:
turning-off the normally-off transistor comprises driving the control node of the normally-off transistor from a first voltage to a second voltage using a first driving circuit; and
reducing the drive voltage of the normally-on transistor comprises decreasing the drive voltage from a third voltage to a fourth voltage using a second driving circuit.

10. The method of claim 9 , wherein the fourth voltage is below a turn-on threshold of the normally-on transistor.

11. The method of claim 1 , wherein turning on the second switch further comprises turning on the second switch a first period of time after turning off the first switch.

12. A circuit comprising:
a first driver terminal configured to be coupled to a control node of a normally-off transistor coupled in series with a normally-on transistor, wherein the normally-off transistor and the normally-on transistor form a first switch coupled between a first switch node and a second switch node;
a second driver terminal configured to be coupled to a control node of a normally-on transistor;
a third driver terminal configured to be coupled to a control node of a second switch coupled between the first switch and a supply node; and
a driver circuit configured to:
turn-on the normally-off transistor via the first driver terminal and turn-on the normally-on transistor via the second driver terminal,
when the first switch conducts a reverse current, turn-off the first switch by turning-off the normally-off transistor via the first driver terminal and reducing a drive voltage of the normally-on transistor via the second driver terminal by decreasing a voltage between the control node of the normally-on transistor and a reference node, wherein the reverse current corresponds to a positive voltage between the second switch node and the first switch node, and the reverse current flows from a source node of the normally-on transistor to a drain node of the normally-on transistor; and
turn on the second switch after turning off the first switch.

13. The circuit of claim 12 , wherein the driver circuit is configured to turn-off the first switch by turning-off the normally-on transistor and reducing the drive voltage of the normally-on transistor at substantially the same time.

14. The circuit of claim 12 , wherein:
the reference node of the normally-on transistor is the source node of the normally-off transistor;
the second switch node is a source node of the normally-off transistor;
and the first switch node is the drain node of the normally-on transistor.

15. The circuit of claim 12 , further comprising the normally-off transistor and the normally-on transistor.

16. The circuit of claim 15 , further comprising the second switch.

17. The circuit of claim 16 , wherein the second switch is coupled between the second switch node and the supply node.

18. The circuit of claim 15 , wherein:
the normally-off transistor comprises an enhancement mode MOSFET; and
the normally-on transistor comprises a gallium nitride (GaN) high electron mobility transistor (HEMT).

19. The circuit of claim 12 , wherein the driver circuit comprises:
a first driver having an output coupled to the first driver terminal; and
a second driver having an output coupled to the second driver terminal.

20. The circuit of claim 12 , wherein the driver circuit comprises:
a first driver having an output coupled to the first driver terminal;
a capacitor coupled between the first driver terminal and the second driver terminal; and
a clamp circuit coupled between the second driver terminal and the second switch node.

21. The circuit of claim 20 , wherein the clamp circuit comprises a diode.

22. The circuit of claim 21 , further comprising a resistor coupled in parallel with the diode.

23. The circuit of claim 22 , wherein:
the first driver is configured to turn the normally-off transistor off for a first period of time; and
a time constant of a capacitance of the capacitor multiplied by a resistance of the resistor is less than the first period of time.

24. The circuit of claim 12 , wherein the driver circuit reduces the drive voltage to a voltage below a threshold of the normally-on transistor.

25. Th

Assignees

• Infineon Technologies Austria Ag

Inventors

• Zojer Bernhard
• Kutschak Matteo-Alessandro

Classifications

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H02M7/219

  in a bridge configuration · CPC title

• H03K2017/6878

  using multi-gate field-effect transistors · CPC title

• H01L27/0629 Primary

  Electricity · mapped topic

• H02M1/4233 Primary

  using a bridge converter comprising active switches · CPC title