Composite semiconductor device

Patent metadata

Field	Value
Publication number	US-9356015-B2
Application number	US-201314418862-A
Country	US
Kind code	B2
Filing date	Jul 29, 2013
Priority date	Aug 28, 2012
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

In a composite semiconductor device which is provided with a normally-on-type first transistor and a normally-off-type second transistor which are serially connected, the second transistor is selected so as to satisfy Formula (1):
C oss > C ds ⁢ V ds V br - C ds - C gs ( 1 )
In this regard: Coss: output capacitance of second transistor Cds: drain to source capacitance of first transistor Cgs: gate to source capacitance of first transistor Vds: power supply voltage Vbr: breakdown voltage of second transistor.

First claim

The invention claimed is:

1. A composite semiconductor device comprising a first transistor of normally on type and a second transistor of normally off type that are connected in series with each other, wherein
a source of the first transistor is connected to a drain of the second transistor,
a gate of the first transistor is connected to a source of the second transistor via a resistor, and
the second transistor meeting a formula (1) is selected:

C
oss

>

C
ds

⁢

V
ds

V
br

-

C
ds

-

C
gs

(
1
)

where Coss: output capacitance of the second transistor, Cds: capacitance between a drain and source of the first transistor, Cgs: capacitance between a gate and the source of the first transistor, Vds: power-source voltage, Vbr: breakdown voltage of the second transistor.

2. A composite semiconductor device comprising a first transistor of normally on type and a second transistor of normally off type that are connected in series with each other, wherein
a source of the first transistor is connected to a drain of the second transistor,
a gate of the first transistor is connected to a source of the second transistor via a resistor, and
the first transistor meeting a formula (2) is selected:

C
ds

<

(

C
oss

+

C
gs

)

⁢

V
br

V
ds

-

V
br

(
2
)

where Coss: output capacitance of the second transistor, Cds: capacitance between a drain and source of the first transistor, Cgs: capacitance between a gate and the source of the first transistor, Vds: power-source voltage, Vbr: breakdown voltage of the second transistor.

3. A composite semiconductor device comprising a first transistor of normally on type and a second transistor of normally off type that are connected in series with each other, wherein
a source of the first transistor is connected to a drain of the second transistor,
a gate of the first transistor is connected to a source of the second transistor via a resistor, and
a ratio between a power source voltage Vds and a breakdown voltage Vbr of the second transistor is 10 or higher, and the second transistor meeting a formula (3) is selected:

C
oss

>

V
ds

V
br

⁢

C
ds

(
3
)

where Coss: output capacitance of the second transistor, Cds: capacitance between a drain and source of the first transistor.

4. A composite semiconductor device comprising a first transistor of normally on type and a second transistor of normally off type that are connected in series with each other, wherein
a source of the first transistor is connected to a drain of the second transistor,
a gate of the first transistor is connected to a source of the second transistor via a resistor, and
a ratio between a power source voltage Vds and a breakdown voltage Vbr of the second transistor is 10 or higher, and the first transistor meeting a formula (4) is selected:

C
ds

<

V
br

V
ds

⁢

C
oss

(
4
)

where Coss: output capacitance of the second transistor, Cds: capacitance between a drain and source of the first transistor.

5. A composite semiconductor device comprising a first transistor of normally on type and a second transistor of normally off type that are connected in series with each other, wherein
a source of the first transistor is connected to a drain of the second transistor,
a gate of the first transistor is connected to a source of the second transistor via a resistor, and
the first transistor and the second transistor that meet a formula (5) are selected:

Assignees

• Sharp Kk

Inventors

• Ohshima Yoshifumi

Classifications

• H10D84/84

  Combinations of enhancement-mode IGFETs and depletion-mode IGFETs · CPC title

• H10D1/47

  Resistors having no potential barriers · CPC title

• H10D84/811 Primary

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H01L27/0629 Primary

  Electricity · mapped topic

• H01L27/0883

  Electricity · mapped topic