Plasma discharge path

Patent metadata

Field	Value
Publication number	US-9793208-B2
Application number	US-201514869963-A
Country	US
Kind code	B2
Filing date	Sep 29, 2015
Priority date	Sep 29, 2015
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

A semiconductor device with a temporary discharge path. During back-end-of-line (BEOL), the temporary discharge path discharges a plasma charge collected in a device well, such as a floating p-type well. After processing, the temporary discharge path is rendered non-function, enabling the device to function properly.

First claim

The invention claimed is:

1. A device comprising:
a semiconductor substrate;
a plurality of interlevel dielectric (ILD) layers disposed on the substrate, wherein each of the ILD layers comprises a metal level and a contact level;
a device region in the substrate, the device region comprises a second polarity type floating well, the floating well is isolated from the substrate by a well isolation region surrounding the floating well;
a first polarity type device disposed in the device region;
a discharge region in the substrate comprising first polarity type dopants, the discharge region is isolated from the floating well by the well isolation region; and
a discharger comprising a fuse unit, wherein the fuse unit is disposed in one of the metal levels of the ILD layers, the fuse unit comprises a fuse array having a plurality of fuses, wherein the plurality of fuses of the fuse unit are horizontally aligned in the same metal level, the discharger comprises a temporary discharge path from the floating well to the discharge region, wherein
the temporary discharge path is configured to discharge plasma charge from the floating well to the discharge region of the substrate during back-end-of-line (BEOL) processing,
the temporary discharge path is configured to enable the first polarity type device to function after completion of the BEOL processing by blowing the plurality of fuses of the fuse unit with a fuse current, and
the plurality of fuses of the fuse unit provides a large discharge path sufficient to dissipate all plasma charges from the floating well to the discharge region of the substrate while maintaining the fuse current below a damage threshold value which negatively impacts interconnect reliability.

2. The device of claim 1 wherein the first polarity type comprises n-type and the second polarity type comprises p-type.

3. The device of claim 1 wherein:
the first polarity type comprises n-type;
the second polarity type comprises p-type;
wherein the first polarity type device comprises a non-volatile memory device.

4. The device of claim 1 wherein the discharger comprises:
a diode having first and second diode terminals, wherein
the first diode terminal comprises a first polarity type doped region disposed in the discharge region, and
the second diode terminal comprises a second polarity type doped region disposed in the floating well;

the fuse unit, wherein the fuse unit comprises
a first fuse terminal,
a second fuse terminal, and
at least one fuse of the fuse array connecting the first and second fuse terminals;

a first fuse unit connector connecting the first fuse terminal and the first diode terminal; and
a second fuse unit connector connecting the second fuse terminal and the second diode terminal.

5. The device of claim 4 wherein the plurality of fuses of the fuse array connects the first and second fuse terminals.

6. The device of claim 4 wherein:
the contact level of each of the ILD layer comprises contacts, and
the metal level of each of the ILD layer comprises metal interconnects; and
the fuse unit is disposed in a fuse metal level which is the metal level of one of the ILD layers.

7. The device of claim 6 wherein the fuse metal level is below an ILD layer of the plurality of ILD layers which incurs plasma damage during the BEOL processing.

8. The device of claim 6 wherein the fuse metal level is a first metal level of a first ILD layer of the plurality of the ILD layers, wherein the first ILD layer is in the closest proximity to the substrate relative to the remainder of the plurality of ILD layers.

9. The device of claim 8 wherein:
the first fuse unit connector comprises a first contact disposed in a first contact level disposed below the first metal level and over the substrate, the first contact connecting the first fuse terminal to the first diode terminal; and
the second fuse unit connector comprises a second contact disposed in the first contact level, the second contact connecting the second fuse terminal to the second diode terminal.

10. The device of claim 4 comprises:
a first test pad coupled to the first fuse terminal;
a second test pad coupled to the second fuse terminal; and
wherein the first and second test pads enable a current to flow through the plurality of fuses of the fuse unit to blow the fuses after completion of the BEOL processing to render the discharger non-functional.

11. The device of claim 1 wherein the well isolation region comprises a first polarity type isolation well surrounding sides and bottom of a second polarity type well to form the second polarity type floating well.

12. A method of forming a device comprising:
providing a semiconductor substrate;
forming a second polarity type floating well in a device region in the substrate, the floating well is isolated from the substrate by a well isolation region surrounding the floating well;
forming a first polarity type doped region in a discharge region of the substrate outside of the floating well, the first polarity type doped region serves as a first diode terminal;
forming a second polarity type doped region in the floating well, the second polarity type doped region serves as a second diode terminal;
completing front-end-of-line (FEOL) processing, including forming a first polarity type device in the device region;
commencing back-end-of-line (BEOL) processing which includes forming a plurality of interlevel dielectric (ILD) levels on the substrate, wherein each of the ILD levels includes a via level with via contacts and a metal level with metal interconnects, and wherein the via level is disposed below the metal level; and
forming a fuse unit having a fuse array in a fuse metal level which is one of the metal levels of the plurality of ILD levels, the fuse array having a plurality of fuses, the plurality of fuses of the fuse unit are horizontally aligned in the same fuse metal level, wherein the fuse unit comprises
a first fuse terminal connected to the first diode terminal,
a second fuse terminal connected to the second diode terminal,
at least one fuse of the fuse array connecting the first and second fuse terminals, and
wherein the fuse unit and diode form a discharger with a temporary discharge path from the floating well to the discharge region,
the temporary discharge path is configured to discharge plasma charge from the floating well to the discharge region of the substrate during the BEOL processing,
the temporary discharge path is configured to enable the first polarity type device to function after completion of the BEOL processing by blowing the plurality of fuses of the fuse unit with a fuse current, and
the plurality of fuses of the fuse unit provides a large discharge path sufficient to dissipating all plasma charges from the floating well to the discharge region of the substrate while maintaining the fuse current below a damage threshold value which negatively impacts interconnect reliability.

13. The method of claim 12 wherein the plurality of fuses of the fuse array connects the first and second fuse terminals.

14. The method of claim 12 wherein the fuse metal level is in a metal level below a metal level which incurs plasma damage during processing.

15. The method of claim 12 wherein the fuse metal level is disposed in a first metal level of a first ILD layer of the plurality of the ILD layers, wherein the first ILD layer is in the closest proximity to the substrate relative to the remainder of the plurality of ILD layers.

16. The method of claim 15 wherein the BEOL processing comprises:
formi

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Sheng Haifeng
• Tan Juan Boon
• Yi Wanbing
• Wang Daxiang
• Siah Soh Yun

Classifications

• H10P50/267

  using plasmas · CPC title

• H10W42/80

  protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/493 Primary

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title

• H01L21/823892

  Electricity · mapped topic