Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction

Patent metadata

Field	Value
Publication number	US-9786661-B2
Application number	US-201615170273-A
Country	US
Kind code	B2
Filing date	Jun 1, 2016
Priority date	May 1, 2014
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.

First claim

What is claimed is:

1. A method of forming a semiconductor device comprising:
forming a fin structure from a semiconductor substrate, wherein an upper surface of the fin structure is provided by an upper surface of the semiconductor substrate and a length of a sidewall of the fin structure extends from the upper surface of the fin structure to a recessed surface of the semiconductor substrate present at a base of the fin structure;
forming an undoped semiconductor material on the fin structure, wherein a first portion of undoped semiconductor material is formed on the sidewall of at least one of a source region portion and a drain region portion of the fin structure, and a second portion of the undoped semiconductor material is formed on the recessed surface of a bulk semiconductor substrate that is present at the base of the fin structure; and
forming a doped epitaxial semiconductor material on the undoped semiconductor material, wherein the undoped semiconductor material and the doped epitaxial semiconductor material provide at least one of a source region and a drain region to the semiconductor device including the fin structure.

2. The method of claim 1 further comprising forming a gate structure on a channel region portion of the fin structure that is between the source region portion and the drain region portion of the fin structure.

3. The method of claim 2 , wherein the gate structure is a replacement gate structure comprised of a sacrificial material, wherein the replacement gate structure is removed after diffusing dopant from the doped epitaxial semiconductor material to the source region portion and the drain region portion of the fin structures; and a functional gate is formed in the place of the replacement gate structure.

4. The method of claim 1 , wherein the forming of the undoped semiconductor material comprises depositing a first thickness of the undoped semiconductor material on an entirety of the sidewall of the source region portion and the drain region portion of the fin structures, and depositing a second thickness of the undoped semiconductor material on the recessed surface of the semiconductor substrate, wherein the second thickness is greater than the first thickness.

5. The method of claim 1 , wherein the forming of the doped epitaxial semiconductor material on the undoped semiconductor material comprises depositing an in situ doped n-type or p-type semiconductor material.

6. The method of claim 5 , wherein an n-type dopant in the in situ doped n-type semiconductor material is present in a concentration ranging from 5×10 20 atoms/cm 3 to 8×10 20 atoms/cm 3 .

7. The method of claim 5 , wherein a p-type dopant in the in situ doped p-type semiconductor material is present in a concentration ranging from 5×10 20 atoms/cm 3 to 8×10 20 atoms/cm 3 .

8. The method of claim 1 further comprising applying a thermal anneal to drive n-type or p-type dopant from the doped epitaxial semiconductor material to the source region portion and the drain region portion of the fin structure.

9. A method of forming a semiconductor device comprising:
forming a plurality of fin structures from a semiconductor substrate, wherein a length of a sidewall for each fin structure of the plurality of fin structures extends from the upper surface of the fin structure to a recessed surface of a semiconductor substrate present between adjacent fin structures of the plurality of fin structures;
forming an undoped semiconductor material on the plurality of fin structures, wherein a first portion of undoped semiconductor material is formed on at least a portion of the sidewall a source region portion and a drain region portion of the plurality of fin structures, and a second portion of the undoped semiconductor material is formed on the recessed surface of a bulk semiconductor substrate that is present between the adjacent fin structures; and
forming a doped semiconductor material on the undoped semiconductor material, wherein the undoped semiconductor material and the doped semiconductor material provide at least one of a merged source region and a merged drain region to the adjacent fin structures of the semiconductor device.

10. The method of claim 9 further comprising forming a gate structure on a channel region portion of the plurality of fin structures that is between the source region portion and the drain region portion of the plurality of fin structures.

11. The method of claim 10 , wherein the gate structure is formed prior to forming the undoped semiconductor material.

12. The method of claim 10 , wherein the gate structure is a replacement gate structure comprised of a sacrificial material, wherein the replacement gate structure is removed after diffusing dopant from the doped semiconductor material to the source region portion and the drain region portion of the plurality of fin structures; and a functional gate is formed in the place of the replacement gate structure.

13. The method of claim 9 , wherein the forming of the undoped semiconductor material comprises depositing a first thickness of the undoped semiconductor material on an entirety of the sidewall of the source region portion and the drain region portion of the plurality of fin structures, and depositing a second thickness of the undoped epitaxial semiconductor material on the recessed surface of the semiconductor substrate present between adjacent fin structures of the plurality of fin structures.

14. The method of claim 13 , wherein the second thickness is greater than the first thickness.

15. The method of claim 7 , wherein the forming of the doped epitaxial semiconductor material on the undoped semiconductor material comprises depositing an in situ doped n-type semiconductor material.

16. The method of claim 9 , wherein the forming of the doped epitaxial semiconductor material on the undoped epitaxial semiconductor material comprises depositing an in situ doped p-type semiconductor material.

17. The method of claim 15 , wherein an n-type dopant in the in situ doped n-type semiconductor material is present in a concentration ranging from 5×10 20 atoms/cm 3 to 8×10 20 atoms/cm 3 .

18. The method of claim 16 , wherein a p-type dopant in the in situ doped p-type semiconductor material is present in a concentration ranging from 5×10 20 atoms/cm 3 to 8×10 20 atoms/cm 3 .

19. The method of claim 7 further comprising applying a thermal anneal to drive the n-type or p-type dopant from the doped epitaxial semiconductor material to the source region portion and the drain region portion of the fin structures.

20. The method of claim 19 , wherein the thermal anneal comprises a temperature ranging from 800° C. to 1200° C.

Assignees

• IBM
• Renesas Electronics Corp

Inventors

• Guo Dechao
• Mochizuki Shogo
• Scholze Andreas
• Yeh Chun-Chen

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P32/1404

  using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase · CPC title

• H10P32/171

  being group IV material · CPC title

• H01L29/66681

  Electricity · mapped topic

• H01L29/08

  Electricity · mapped topic