Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction

Patent metadata

Field	Value
Publication number	US-9390976-B2
Application number	US-201514610653-A
Country	US
Kind code	B2
Filing date	Jan 30, 2015
Priority date	May 1, 2014
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

A method of forming a semiconductor device that includes forming a fin structure, and forming an undoped epitaxial semiconductor material on the fin structure. A first portion of undoped epitaxial semiconductor material is formed on the sidewall of at least one of a source region portion and a drain region portion of the fin structure. A second portion of the undoped epitaxial semiconductor material is formed on the recessed surface of a bulk semiconductor substrate that is present at the base of the fin structure. The method further includes forming a doped epitaxial semiconductor material on the undoped epitaxial semiconductor material. The undoped epitaxial semiconductor material and the doped epitaxial semiconductor material provide a source region and drain region.

First claim

What is claimed is:

1. A method of forming a semiconductor device comprising:
forming a fin structure from a bulk semiconductor substrate, wherein an upper surface of the fin structure is provided by an upper surface of the bulk semiconductor substrate and a length of a sidewall of the fin structure extends from the upper surface of the fin structure to a recessed surface of the bulk semiconductor substrate present at a base of the fin structure;
forming an undoped epitaxial semiconductor material on the fin structure, wherein a first portion of undoped epitaxial semiconductor material is formed on the sidewall of at least one of a source region portion and a drain region portion of the fin structure, and a second portion of the undoped epitaxial semiconductor material is formed on the recessed surface of the bulk semiconductor substrate that is present at the base of the fin structure; and
forming a doped epitaxial semiconductor material on the undoped epitaxial semiconductor material, wherein the undoped epitaxial semiconductor material and the doped epitaxial semiconductor material provide a source region and drain region to the semiconductor device including the fin structure.

2. The method of claim 1 further comprising forming a gate structure on a channel region portion of the fin structure that is between the source region portion and the drain region portion of the fin structure.

3. The method of claim 2 , wherein the gate structure is a replacement gate structure comprised of a sacrificial material, wherein the replacement gate structure is removed after diffusing dopant from the doped epitaxial semiconductor material to the source region portion and the drain region portion of the fin structures; and a functional gate is formed in the place of the replacement gate structure.

4. The method of claim 1 , wherein the forming of the undoped epitaxial semiconductor material comprises depositing a first thickness of the undoped epitaxial semiconductor material on an entirety of the sidewall of the source region portion and the drain region portion of the fin structures, and depositing a second thickness of the undoped epitaxial semiconductor material on the recessed surface of the bulk semiconductor substrate, wherein the second thickness is greater than the first thickness.

5. The method of claim 1 , wherein the forming of the doped epitaxial semiconductor material on the undoped epitaxial semiconductor material comprises depositing an in situ doped n-type or p-type semiconductor material, wherein an n-type or p-type dopant in the in situ doped n-type or p-type semiconductor material is present in a concentration ranging from 5×10 20 atoms/cm 3 to 8×10 20 atoms/cm 3 .

6. The method of claim 1 further comprising applying a thermal anneal to drive n-type or p-type dopant from the doped epitaxial semiconductor material to the source region portion and the drain region portion of the fin structure.

7. A method of forming a semiconductor device comprising:
forming a plurality of fin structures from a bulk semiconductor substrate, wherein a length of a sidewall for each fin structure of the plurality of fin structures extends from the upper surface of the fin structure to a recessed surface of a bulk semiconductor substrate present between adjacent fin structures of the plurality of fin structures;
forming an undoped epitaxial semiconductor material on the plurality of fin structures, wherein a first portion of undoped epitaxial semiconductor material is formed on at least a portion of the sidewall of a source region portion and a drain region portion of the plurality of fin structures, and a second portion of the undoped epitaxial semiconductor material is formed on the recessed surface of the bulk semiconductor substrate that is present between the adjacent fin structures; and
forming a doped epitaxial semiconductor material on the undoped epitaxial semiconductor material, wherein the undoped epitaxial semiconductor material and the doped epitaxial semiconductor material provide a merged source region and a merged drain region to the adjacent fin structures of the semiconductor device.

8. The method of claim 7 further comprising forming a gate structure on a channel region portion of the plurality of fin structures that is between the source region portion and the drain region portion of the plurality of fin structures, wherein the gate structure is formed prior to forming the undoped epitaxial semiconductor material.

9. The method of claim 8 , wherein the gate structure is a replacement gate structure comprised of a sacrificial material, wherein the replacement gate structure is removed after diffusing dopant from the doped epitaxial semiconductor material to the source region portion and the drain region portion of the plurality of fin structures; and a functional gate is formed in the place of the replacement gate structure.

10. The method of claim 7 , wherein the forming of the undoped epitaxial semiconductor material comprises depositing a first thickness of the undoped epitaxial semiconductor material on an entirety of the sidewall of the source region portion and the drain region portion of the plurality of fin structures, and depositing a second thickness of the undoped epitaxial semiconductor material on the recessed surface of the bulk semiconductor substrate present between adjacent fin structures of the plurality of fin structures, wherein the second thickness is greater than the first thickness.

11. The method of claim 7 , wherein the forming of the doped epitaxial semiconductor material on the undoped epitaxial semiconductor material comprises depositing an in situ doped n-type or p-type semiconductor material, wherein an n-type or p-type dopant in the in situ doped n-type or p-type semiconductor material is present in a concentration ranging from 5×10 20 atoms/cm 3 to 8×10 20 atoms/cm 3 .

12. The method of claim 7 further comprising applying a thermal anneal to drive the n-type or p-type dopant from the doped epitaxial semiconductor material to the source region portion and the drain region portion of the fin structures.

Assignees

• IBM
• Renesas Electronics Corp

Inventors

• Guo Dechao
• Mochizuki Shogo
• Scholze Andreas
• Yeh Chun-Chen

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P32/1404

  using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase · CPC title

• H10P32/171

  being group IV material · CPC title

• H10D62/832

  being Group IV materials comprising two or more elements, e.g. SiGe · CPC title

• H10D62/82

  Heterojunctions · CPC title