Selective removal of charge-trapping layer for select gate transistor and dummy memory cells in 3D stacked memory

Patent metadata

Field	Value
Publication number	US-9490262-B1
Application number	US-201615143922-A
Country	US
Kind code	B1
Filing date	May 2, 2016
Priority date	Apr 20, 2015
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

Fabrication techniques for a three-dimensional stack memory device remove the charge-trapping material from the select gate transistors and the dummy memory cells to avoid unintentional programming which increases the threshold voltage. In one approach, a stack is formed with a sacrificial material for the a) control gate layers of the select gate transistors and the dummy memory cells and the b) control gate layers of the data memory cells. A slit is formed to allow etchants to be introduced to selectively remove the sacrificial material and then the charge-trapping material for the select gate transistors and dummy memory cells. A protective layer is provided partway in the slit, or the slit is etched in two steps.

First claim

What is claimed is:

1. A method for fabricating a memory device, comprising:
forming a stack comprising alternating control gate layers and dielectric layers, the control gate layers of the stack comprise a control gate layer for a first transistor above control gate layers for data memory cells;
forming a memory hole in the stack, the memory hole having a sidewall;
depositing a charge-trapping material, a tunneling material and a channel material along the sidewall, wherein the charge-trapping material is deposited before the tunneling material, and the tunneling material is deposited before the channel material;
etching a slit in the stack;
depositing a protective layer in the slit;
etching down the protective layer to a height in the stack which is between the control gate layer for the first transistor and the control gate layers for the data memory cells, exposing a sacrificial material of the control gate layer for the first transistor to the slit and leaving a remaining portion of the protective layer which shields a sacrificial material of the control gate layers for the data memory cells from the slit;
providing an etchant in the slit which etches away the sacrificial material of the control gate layer for the first transistor, creating a void in the control gate layer for the first transistor and exposing a portion of the charge-trapping material in the control gate layer for the first transistor;
providing an etchant in the slit to etch away the portion of the charge-trapping material which is in the control gate layer for the first transistor;
providing an etchant in the slit which etches away the remaining portion of the protective layer, exposing the sacrificial material of the control gate layers for the data memory cells to the slit;
providing an etchant in the slit which etches away the sacrificial material of the control gate layers for the data memory cells, creating voids in the control gate layers for the data memory cells;
depositing a metal in the slit, the metal fills the void in the control gate layer for the first transistor and the voids in the control gate layers for the data memory cells, wherein portions of the charge-trapping material in the control gate layers for the data memory cells remain in the memory device; and
providing a blocking oxide layer between the charge-trapping material and the metal.

2. The method of claim 1 , wherein:
the control gate layer for the first transistor and the control gate layers for the data memory cells comprises a common sacrificial material.

3. The method of claim 1 , wherein:
the sacrificial material of the control gate layer for the first transistor and the sacrificial material of the control gate layers for the data memory cells comprise silicon nitride.

4. The method of claim 1 , wherein:
the first transistor comprises a select gate transistor.

5. The method of claim 1 , wherein:
the first transistor comprises a dummy memory cell.

6. The method of claim 1 , further comprising:
performing ion implantation at a top of the stack to provide a dopant in the channel material, the dopant is provided at a portion of the channel material which is in the control gate layer for the first transistor.

7. The method of claim 1 , further comprising:
after the providing the etchant to etch away the portion of the charge-trapping material which is in the control gate layer for the first transistor, providing a dopant in the void in the control gate layer for the first transistor to expose the portion of the channel material in the control gate layer for the first transistor to the dopant.

8. The method of claim 1 , wherein:
the providing the blocking oxide layer comprises depositing the blocking oxide layer via the slit, and the blocking oxide layer extends in the void in the control gate layer for the first transistor and in the voids in the control gate layers for the data memory cells.

9. The method of claim 1 , wherein the providing the blocking oxide layer comprises depositing the blocking oxide layer along the sidewall before the depositing of the charge-trapping material, the method further comprising:
before the providing the etchant in the slit to etch away the portion of the charge-trapping material which is in the control gate layer for the first transistor, providing an etchant in the slit and in the void in the control gate layer for the first transistor to etch away a portion of the blocking oxide layer in the control gate layer for the first transistor.

10. The method of claim 9 , further comprising:
providing an etchant in the slit and in the void in the control gate layer for the first transistor to etch away a portion of the blocking oxide layer which is in the control gate layer for the first transistor, before the providing the etchant in the slit to etch away the portion of the charge-trapping material which is in the control gate layer for the first transistor.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Pang Liang
• Dong Yingda

Classifications

• H10P50/667

  by liquid etching only · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title