Nonvolatile memory device and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-9490429-B2
Application number	US-201514860349-A
Country	US
Kind code	B2
Filing date	Sep 21, 2015
Priority date	Dec 6, 2010
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.

First claim

The invention claimed is:

1. A method for manufacturing a nonvolatile storage device, comprising the steps of:
(a) forming, on a semiconductor substrate, a first conductive layer extended in a first direction along a main surface of the semiconductor substrate;
(b) forming, on the first conductive layer, a stacked film in which (N+1) (N is an integer of N≧1) first insulator films and N second conductive layers are alternately stacked together;
(c) forming a third conductive layer on the stacked film;
(d) forming a second insulator film on a side wall of the stacked film, and forming a first semiconductor layer and a memory material layer, which are electrically connected to the third conductive layer, on a sidewall of the second insulator film including on a portion of said second insulator film which extends beyond and is not in contact with the stacked film; and
(e) after the step (d), forming, on the third conductive layer, a fourth conductive layer electrically connected to the third conductive layer, and extended in a second direction orthogonal to the first direction.

2. The method for manufacturing a nonvolatile storage device according to claim 1 , wherein in the step (d), the second insulator film is formed so that a height of an uppermost surface of the second insulator film is located in a region lower than a bottom surface of the third conductive layer, and higher than an uppermost surface of the second conductive layer of an uppermost layer.

3. The method for manufacturing a nonvolatile storage device according to claim 1 , wherein the step (d) comprises:
(d1) forming the second insulator film to cover the stacked film and the third conductive layer;
(d2) forming a second semiconductor layer on the sidewall of the stacked film through the second insulator film;
(d3) removing the second insulator film exposed from the second semiconductor layer; and
(d4) forming the first semiconductor layer and the memory material layer on the sidewall of the stacked film through the second insulator film and the second semiconductor layer.

4. The method for manufacturing a nonvolatile storage device according to claim 1 ,
wherein in the step (a), a fifth conductive layer, a semiconductor layer of a first conductivity type, and a semiconductor layer of a second conductivity type are stacked on the semiconductor substrate in order from the semiconductor substrate side, and then a semiconductor layer of the second conductivity type, a semiconductor layer of the first conductivity type, and the fifth conductive layer are processed into a plurality of first patterns extended in the first direction and aligned in the second direction to form the first conductive layer formed of the fifth conductive layer,
wherein in the step (b), the stacked film is deposited on the semiconductor layer of the second conductivity type, and
wherein the method further comprises the step of:
(a1), after the step (a), dividing a structure having the semiconductor layer of the second conductivity type and the semiconductor layer of the first conductivity type to form a plurality of the structures at given intervals in the first direction.

5. The method for manufacturing a nonvolatile storage device according to claim 1 ,
wherein in the step (a), a plurality of the first conductive layers is formed to be aligned in the second direction,
wherein in the step (d), the second insulator film, the first semiconductor layer, and the memory material layer are formed on each of the facing sidewalls of the adjacent stacked films in the second direction,
wherein in the step (e), a plurality of the fourth conductive layers is formed to be aligned in the first direction, the method further comprises the steps of:
(c1) before the step (d), processing the stacked film and the third conductive layer into a plurality of second patterns extended in the first direction and aligned in the second direction;
(c5) before the step (e), embedding a third insulator film between the adjacent memory material layers formed on the respective sidewalls of the facing stacked films; and
(e1) removing the first semiconductor layer and the memory material layer immediately below regions between the adjacent fourth conductive layers in the first direction.

6. The method for manufacturing a nonvolatile storage device according to claim 1 , further comprising the step of:
(c2) before the step (d), forming a hole penetrating through the stacked film and the third conductive layer immediately above the first conductive layer,
wherein in the step (d), the second insulator film, the first semiconductor layer, and the memory material layer are formed within the hole and on the sidewall of the stacked film.

7. The method for manufacturing a nonvolatile storage device according to claim 1 ,
wherein in the step (d), the second insulator film, the first semiconductor layer, and the memory material layer are formed in order from the sidewall of the stacked film.

Assignees

• Hitachi Ltd

Inventors

• Sasago Yoshitaka
• Kinoshita Masaharu
• Tai Mitsuharu
• Shima Akio
• Kurotsuchi Kenzo
• Kobayashi Takashi

Classifications

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C2213/75

  Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor · CPC title

• H10D88/00 Primary

  Three-dimensional [3D] integrated devices · CPC title

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H01L45/06

  Electricity · mapped topic