Continuous time delta sigma modulator, analog to digital converter and associated compensation method

Patent metadata

Field	Value
Publication number	US-9537497-B2
Application number	US-201615044125-A
Country	US
Kind code	B2
Filing date	Feb 16, 2016
Priority date	May 14, 2015
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

A continuous time delta sigma modulator includes a summing circuit, a loop filter, an extraction circuit, a quantizer and a digital to analog converter. The summing circuit is arranged for subtracting a feedback signal by an input signal to generate a residual signal. The loop filter includes a plurality of amplifying stages connected in series and is arranged to receive the residual signal to generate a filtered residual signal. The extraction circuit is arranged for extracting a current from one of the amplifying stages and forwarding the extracted current to a following one of the amplifying stages. The quantizer is arranged for generating a digital output signal according to the filtered residual signal. The digital to analog converter is arranged for performing a digital to analog converting operation upon a signal derived from the digital output signal to generate the feedback signal to the summing circuit.

First claim

What is claimed is:

1. A continuous time delta sigma modulator, comprising:
a first summing circuit, for subtracting a feedback signal by an input signal to generate a residual signal;
a loop filter comprising a plurality of amplifying stages connected in series and arranged to receive the residual signal to generate a filtered residual signal;
an extraction circuit, coupled to the loop filter, for extracting a current from one of the amplifying stages and forwarding the extracted current to a following one of the amplifying stages;
a quantizer, coupled to the loop filter, for generating a digital output signal according to the filtered residual signal; and
a digital to analog converter, coupled to the quantizer and the first summing circuit, for performing a digital to analog converting operation upon a signal derived from the digital output signal to generate the feedback signal to the first summing circuit;
wherein the extraction circuit mirrors an output current of the one of the amplifying stages to generate the extracted current, and forwards the extracted current to the following one of the amplifying stages.

2. The continuous time delta sigma modulator of claim 1 , wherein the extraction circuit forwards the extracted current to an output node of the following one of the amplifying stages.

3. The continuous time delta sigma modulator of claim 1 , wherein the extraction circuit mirrors the current from a first one of the amplifying stages and forwards the extracted current to a last one of the amplifying stages.

4. The continuous time delta sigma modulator of claim 1 , wherein the extracted current and an output current of a last amplifying stage of the loop filter are combined to generate the filtered residual signal.

5. The continuous time delta sigma modulator of claim 1 , wherein the extracted current forwarded to the following one of the amplifying stages is used to compensate a coefficient of the following one of the amplifying stages; and compensations of the amplifying stages are not involved with any other digital to analog converter.

6. The continuous time delta sigma modulator of claim 1 , wherein the loop filter further comprises a compensation resistor coupled to an output node of the following one of the amplifying stages, and the extraction circuit directly forwards the extracted current to the following one of the amplifying stages via the compensation resistor.

7. The continuous time delta sigma modulator of claim 1 , wherein the extraction circuit extracts currents from two or more amplifying stages, and forwards the currents to the following one of the amplifying stages.

8. A compensation method of an analog to digital converter, comprising:
subtracting a feedback signal by an input signal to generate a residual signal;
providing a loop filter comprising residual a plurality of amplifying stages connected in series and arranged to receive the residual signal to generate a filtered residual signal;
extracting a current from one of the amplifying stages and forwarding the extracted current to a following one of the amplifying stages to compensate a loop delay of the analog to digital converter;
generating a digital output signal according to the filtered residual signal; and
performing a digital to analog converting operation upon a signal derived from the digital output to generate the feedback signal;
wherein the step of extracting the current from the output current of the one of the amplifying stages and forwarding the extracted current to the following one of the amplifying stages comprises:
mirroring the output current of the one of the amplifying stages to generate the extracted current, and forwarding the extracted current to the following one of the amplifying stages.

9. The compensation method of claim 8 , wherein the step of extracting the current from the output current of the one of the amplifying stages and forwarding the extracted current to the following one of the amplifying stages comprises:
forwarding the extracted current to an output node of the following one of the amplifying stages.

10. The compensation method of claim 8 , wherein the step of extracting the current from the one of the amplifying stages and forwarding the extracted current to the following one of the amplifying stages comprises:
mirroring the current from a first one of the amplifying stages and forwarding the extracted current to a last one of the amplifying stages.

11. The compensation method of claim 8 , further comprising:
combining the extracted current and an output current of a last amplifying stage of the loop filter to generate the filtered residual signal.

12. The compensation method of claim 8 , wherein the feedback signal is generated by a digital to analog converter, and compensations of the amplifying stages are not involved with any other digital to analog converter.

13. The compensation method of claim 8 , wherein the loop filter further comprises a compensation resistor coupled to an output node of the following one of the amplifying stages, and the step of extracting the current from the one of the amplifying stages and forwarding the extracted current to the following one of the amplifying stages comprises:
directly forwarding the extracted current to the following one of the amplifying stages via the compensation resistor.

14. The compensation method of claim 8 , wherein the step of extracting the current from the one of the amplifying stages and forwarding the extracted current to the following one of the amplifying stages comprises:
extracting currents from two or more amplifying stages, and forwarding the currents to the following one of the amplifying stages.

15. A continuous time delta sigma modulator, comprising:
a first summing circuit, for subtracting a feedback signal by an input signal to generate a residual signal;
a loop filter comprising a plurality of amplifying stages connected in series and arranged to receive the residual signal to generate a filtered residual signal;
an extraction circuit, coupled to the loop filter, for extracting a current from one of the amplifying stages and forwarding the extracted current to a following one of the amplifying stages;
a quantizer, coupled to the loop filter, for generating a digital output signal according to the filtered residual signal; and
a digital to analog converter, coupled to the quantizer and the first summing circuit, for performing a digital to analog converting operation upon a signal derived from the digital output signal to generate the feedback signal to the first summing circuit;
wherein the extracted current forwarded to the following one of the amplifying stages is used to compensate a coefficient of the following one of the amplifying stages; and compensations of the amplifying stages are not involved with any other digital to analog converter.

16. The continuous time delta sigma modulator of claim 15 , wherein the extraction circuit extracts the current from an output current of the one of the amplifying stages and forwards the extracted current to the following one of the amplifying stages.

17. The continuous time delta sigma modulator of claim 16 , wherein the extraction circuit mirrors the output current of the one of the amplifying stages to generate the extracted current, and forwards the extracted current to the following one of the amplifying stages.

18. The continuous time delta sigma modulator of claim 16 , wherein the extraction circuit extracts the current from the output current of the one of the amplifying stage

Assignees

• Mediatek Inc

Inventors

• Ho Chen-Yen
• Lin Yu-Hsin
• Wang Tze-Chien

Classifications

• H03M3/422

  having one quantiser only · CPC title

• H03M1/06 Primary

  Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, {e.g. by using stored correction values,} H03M1/10) · CPC title

• H03M3/464 Primary

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/37

  Compensation or reduction of delay or phase error · CPC title

• H03M3/39 Primary

  Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators (of digital delta-sigma modulators H03M7/3004) · CPC title