Device without zero mark layer

Patent metadata

Field	Value
Publication number	US-9773702-B2
Application number	US-201514981873-A
Country	US
Kind code	B2
Filing date	Dec 28, 2015
Priority date	Dec 29, 2014
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.

First claim

What is claimed is:

1. A method for forming a device comprising:
providing a substrate having a top and a bottom surface, wherein the substrate is defined with a device region and a frame region surrounding the device region, wherein the frame region comprises wafer dicing channels;
forming at least one through silicon via (TSV) opening in the substrate, wherein the TSV opening extends through the top and bottom surfaces of the substrate;
forming an alignment trench corresponding to an alignment mark in the substrate, wherein the alignment trench extends from the top surface of the substrate to a depth shallower than a depth of the TSV opening;
providing a dielectric liner over the top surface of the substrate, wherein the dielectric liner is a single continuous dielectric layer which lines sidewalls of the TSV opening and extends over the substrate to completely cover a bottom and sidewalls of the alignment trench;
providing a conductive layer over the dielectric liner, wherein the conductive layer fills the TSV opening;
processing the conductive layer to form a TSV contact within the TSV opening, wherein a top surface of the TSV contact is coplanar with a top surface of the dielectric liner;
forming a first redistribution layer (RDL) over the dielectric liner and the TSV contact, wherein the first RDL layer comprises a dielectric material and a contact pad opening, wherein the contact pad opening extends through the first RDL layer to completely expose the top surface of the TSV contact, wherein a portion of the first RDL layer overlaps the alignment trench; and
forming a TSV contact pad in the contact pad opening of the first RDL layer, wherein a top surface of the TSV contact pad is coplanar with a top surface of the first RDL layer.

2. The method of claim 1 wherein the TSV opening and the alignment trench are formed simultaneously in the substrate, wherein the TSV opening is formed in the device region and the alignment trench is formed in the frame region.

3. The method of claim 1 wherein the alignment trench comprises a width less than about 2 times the thickness of the dielectric liner which lines the sidewalls of the TSV opening.

4. The method of claim 1 comprising forming the alignment mark in the alignment trench prior to forming the first RDL layer, wherein the alignment mark is devoid of conductive material.

5. The method of claim 1 wherein the dielectric liner completely fills the alignment trench to form the alignment mark.

6. The method of claim 1 wherein the dielectric liner which lines the alignment trench pinches off to form the alignment mark having a closed-off void within the alignment trench.

7. The method of claim 6 wherein the alignment mark is devoid of conductive material.

8. The method of claim 1 wherein a portion of the dielectric liner extends over the alignment trench, wherein the portion of the first RDL layer which overlaps the alignment trench is in contact with the portion of the dielectric liner which extends over the alignment trench.

9. The method of 1 comprising forming a second RDL layer over the first RDL layer, wherein the second RDL layer is processed to form an interconnect structure in the second RDL layer, wherein the interconnect structure comprises a conductive contact and a conductive line.

10. The method of claim 9 wherein the interconnect structure in the second RDL layer is in electrical communication with the TSV contact pad in the first RDL layer, wherein the first and second RDL layers are dielectric layers.

11. A method for forming a device comprising:
providing a substrate having a top and a bottom surface, wherein the substrate is defined with a device region and a frame region surrounding the device region, wherein the frame region comprises wafer dicing channels;
forming a through silicon via (TSV) opening and an alignment trench corresponding to an alignment mark in the substrate, wherein the TSV opening is formed within the device region and the alignment trench is formed within the frame region, wherein the alignment trench extends from the top surface of the substrate to a depth shallower than a depth of the TSV opening;
providing a dielectric liner over the top surface of the substrate, wherein the dielectric liner is a single continuous layer which at least lines sidewalls of the TSV opening and extends over the first surface of the substrate to completely cover a bottom and sidewalls of the alignment trench;
providing a conductive layer over the dielectric liner, wherein the conductive layer fills the TSV opening;
processing the conductive layer to form a TSV contact in the TSV opening, wherein a top surface of the TSV contact is coplanar with a top surface of the dielectric liner;
forming a first redistribution layer (RDL) over the dielectric liner, wherein the first RDL layer comprises a contact pad opening extending through the first RDL layer, wherein the contact pad opening exposes the top surface of the TSV contact, wherein a portion of the first RDL layer completely overlaps the alignment trench; and
forming a TSV contact pad in the contact pad opening of the first RDL layer.

12. The method of claim 11 comprising:
forming a second RDL layer over the first RDL layer, wherein the second RDL layer is processed to form an interconnect structure within the second RDL layer, wherein the interconnect structure in the second RDL layer is in electrical communication with the TSV contact pad in the first RDL layer.

13. The method of claim 12 comprising forming the alignment mark in the alignment trench prior to forming the first RDL layer, wherein the alignment mark is electrically isolated from the TSV contact pad in the first RDL layer and the interconnect structure in the second RDL layer.

14. The method of claim 11 wherein the dielectric liner extends over the alignment trench to form a closed-off void within the alignment trench.

15. The method of claim 11 wherein the dielectric liner lines the bottom and sidewalls of the alignment trench without filling the alignment trench.

16. The method of 15 wherein the conductive layer which fills the TSV opening to form the TSV contact also fills the alignment trench to form the alignment mark, wherein the alignment mark is electrically isolated from the TSV contact and the TSV contact pad.

17. The method of claim 11 comprising forming the alignment mark in the alignment trench prior to forming the first RDL layer, wherein the alignment mark is devoid of conductive material.

18. The method of claim 16 comprising processing the conductive layer to form the alignment mark such that a top surface of the alignment mark is coplanar with the top surface of the dielectric liner and the top surface of the TSV contact.

19. The method of claim 11 wherein a portion of the dielectric liner extends over the alignment trench, wherein the portion of the first RDL layer which overlaps the alignment trench is in contact with the portion of the dielectric liner which extends over the alignment trench.

20. The method of claim 11 comprising forming a hard mask layer on the top surface of the substrate and a soft mask layer on the hard mask layer prior to forming the TSV opening and the alignment trench, wherein the soft mask is patterned to expose a first and a second portion of the hard mask layer, wherein the first exposed portion corresponds with the location of the alignment trench and the second exposed portion corresponds with the location of the TSV opening.

21. The method of

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Gong Shunqiang
• Tan Juan Boon
• Wang Shijie
• Bhatkar Mahesh
• Wang Daxiang

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W46/501

  for use before dicing · CPC title

• H10W46/301

  for alignment · CPC title

• H10W46/101

  characterised by the type of information, e.g. logos or symbols · CPC title

• H10W20/49

  Adaptable interconnections, e.g. fuses or antifuses · CPC title