FinFET with insulator under channel

Patent metadata

Field	Value
Publication number	US-9224865-B2
Application number	US-201313945627-A
Country	US
Kind code	B2
Filing date	Jul 18, 2013
Priority date	Jul 18, 2013
Publication date	Dec 29, 2015
Grant date	Dec 29, 2015

Abstract

A FinFET has a structure including a semiconductor substrate, semiconductor fins and a gate spanning the fins. The fins each have a bottom region coupled to the substrate and a top active region. Between the bottom and top fin regions is a middle stack situated between a vertically elongated source and a vertically elongated drain. The stack includes a top channel region and a dielectric region immediately below the channel region, providing electrical isolation of the channel. The partial isolation structure can be used with both gate first and gate last fabrication processes.

First claim

The invention claimed is:

1. A method, comprising:
providing a semiconductor structure, the structure comprising:
a bulk semiconductor substrate; and
at least one semiconductor fin, each fin comprising a top active region, a bottom region coupled to the substrate, and a dielectric region directly below the top region and above the bottom region, wherein a dielectric of the dielectric region encases the bottom region and the dielectric region;

building a gate spanning the at least one fin over a channel region thereof;
recessing areas of the top active region and the dielectric region on either side of the channel region after building the gate, such that the dielectric region remains only under the channel region; and
creating a source and a drain in the recessed areas.

2. The method of claim 1 , further comprising, prior to the recessing:
conformally depositing a layer of a sidewall spacer material over the gate; and
etching spacers on either side of the gate from the sidewall spacer layer.

3. The method of claim 1 , wherein building the gate comprises:
depositing a gate dielectric layer over the top active region of the at least one fin;
depositing a gate metal layer over the gate dielectric layer; and depositing a gate electrode material over the gate metal layer.

4. The method of claim 1 , wherein building the gate comprises building a dummy gate, the method further comprising replacing the dummy gate with a metal gate after creating the source and drain.

5. The method of claim 1 , wherein creating the source and the drain comprises vertically extending the source and the drain higher than a top surface of the top active region of the at least one fin.

6. The method of claim 1 , wherein the recessing further comprises recessing through a portion of the bottom region of the at least one fin, and wherein creating the source and the drain comprises epitaxially growing the source and the drain on a remaining portion of the bottom region.

7. The method of claim 6 , wherein the epitaxially growing comprises creating a lattice mismatch with the channel region to induce stress into the channel region.

8. The method of claim 7 , wherein creating the lattice mismatch comprises:
removing the epitaxy of the source and drain; and
regrowing the source and drain epitaxy.

9. The method of claim 1 , wherein the semiconductor substrate, the top active region and the bottom region comprise silicon, and wherein the dielectric comprises one of silicon dioxide, germanium oxide and germanium crystals embedded in silicon dioxide.

Assignees

• Globalfoundries Inc

Inventors

• Akarvardar Murat Kerem
• Fronheiser Jody A
• Jacob Ajey Poovannummoottil

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title