Method, apparatus and system for responding to a row hammer event

Patent metadata

Field	Value
Publication number	US-9761298-B2
Application number	US-201615364123-A
Country	US
Kind code	B2
Filing date	Nov 29, 2016
Priority date	Dec 21, 2012
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.

First claim

What is claimed is:

1. An apparatus comprising a memory controller, the memory controller comprising:
a hardware interface to couple the memory controller to a dynamic random access memory (DRAM) device, the DRAM device including a bank of memory; and
command logic to issue multiple commands to the DRAM device in response to a number of accesses to a target row of the bank meets or exceeds a threshold within a time interval, the multiple commands including:
a mode register set (MRS) command to set one or more configuration bits of a mode register of the DRAM device to trigger entry of the DRAM device into a targeted row refresh (TRR) mode;
a first Activation command to be directed to a bank group including the target row when the DRAM device is in the TRR mode;
a first Precharge command corresponding to the first Activation command to be issued at least a delay of (1.5*tRAS) after the first Activation command, wherein tRAS is a row active timing parameter; and
two additional Activation commands and corresponding additional Precharge commands,

wherein the multiple commands are to refresh at least one victim row physically proximate to the target row.

2. The apparatus of claim 1 , wherein the mode register comprises Mode Register 2 (MR2).

3. The apparatus of claim 1 , further comprising the command logic to delay issuance of other commands to the DRAM device for a mode register set command delay period of tMOD in conjunction with issuance of the MRS command to maintain the DRAM device inactive for at least tMOD.

4. The apparatus of claim 1 , wherein the DRAM device includes a synchronous DRAM (SDRAM) device compliant with a dual data rate version 4 (DDR4) standard.

5. The apparatus of claim 1 , further comprising:
a DRAM device communicatively coupled to the memory controller, the DRAM device including the bank with the target row.

6. The apparatus of claim 5 , wherein the DRAM device is to automatically exit the TRR mode after refresh of the at least one victim row.

7. The apparatus of claim 6 , wherein the DRAM device is to count the Activation commands issued, and in response to detection of refresh of the at least one victim row, automatically clear a TRR mode configuration setting from the mode register set by the MRS command.

8. The apparatus of claim 6 , wherein the command logic to further automatically delay by at least a mode register set command delay period of tMOD in conjunction with exit of the DRAM device from the TRR mode.

9. The apparatus of claim 5 , further comprising one or more of:
at least one processor communicatively coupled to the memory controller;
a display communicatively coupled to display data from the DRAM device;
a battery to power the apparatus; or
a network interface communicatively coupled to exchange data stored in the DRAM device with a remote device over a network connection.

10. The apparatus of claim 1 , wherein physically proximate comprises physically adjacent.

11. The apparatus of claim 1 , wherein the command logic is to issue only activate and precharge commands to the bank group while the DRAM device is in the TRR mode.

12. The apparatus of claim 1 , further comprising:
row hammer detect logic to detect that access to the target row meets or exceeds the threshold within the time interval.

13. The apparatus of claim 12 , wherein the memory controller comprises the row hammer detect logic.

14. The apparatus of claim 12 , further comprising the DRAM device coupled to the memory controller, wherein the DRAM device comprises the row hammer detect logic.

15. The apparatus of claim 1 , wherein the memory controller comprises an integrated memory controller, integrated with a processor device.

16. An apparatus comprising:
a processor; and
a memory controller communicatively coupled to the processor, the memory controller including command logic to issue multiple commands to a dynamic random access memory (DRAM) device when coupled, and in response to a number of accesses to a target row of a bank of the DRAM device meets or exceeds a threshold within a time interval, the multiple commands including:
a mode register set (MRS) command to set one or more configuration bits of a mode register of the DRAM device to trigger entry of the DRAM device into a targeted row refresh (TRR) mode;
a first Activation command to be directed to a bank group including the target row when the DRAM device is in the TRR mode;
a first Precharge command corresponding to the first Activation command to be issued at least a delay of (1.5*tRAS) after the first Activation command, wherein tRAS is a row active timing parameter; and
two additional Activation commands and corresponding additional Precharge commands,

wherein the multiple commands are to refresh at least one victim row physically proximate to the target row.

17. The apparatus of claim 16 , wherein the mode register comprises Mode Register 2 (MR2).

18. The apparatus of claim 16 , further comprising the command logic to delay issuance of other commands to the DRAM device for a mode register set command delay period of tMOD in conjunction with issuance of the MRS command to maintain the DRAM device inactive for at least tMOD.

19. The apparatus of claim 16 , wherein the DRAM device includes a synchronous DRAM (SDRAM) device compliant with a dual data rate version 4 (DDR4) standard.

20. The apparatus of claim 16 , further comprising:
a DRAM device communicatively coupled to the memory controller, the DRAM device including the bank with the target row.

21. The apparatus of claim 20 , wherein the DRAM device is to automatically exit the TRR mode after refresh of the at least one victim row.

22. The apparatus of claim 21 , wherein the DRAM device is to count the Activation commands issued, and in response to detection of refresh of the at least one victim row, automatically clear a TRR mode configuration setting from the mode register set by the MRS command.

23. The apparatus of claim 21 , wherein the command logic to further automatically delay by at least a mode register set command delay period of tMOD in conjunction with exit of the DRAM device from the TRR mode.

24. The apparatus of claim 20 , further comprising one or more of:
a display communicatively coupled to display data from the DRAM device;
a battery to power the apparatus; or
a network interface communicatively coupled to exchange data stored in the DRAM device with a remote device over a network connection.

25. The apparatus of claim 16 , wherein physically proximate comprises physically adjacent.

26. The apparatus of claim 16 , wherein the command logic is to issue only activate and precharge commands to the bank group while the DRAM device is in the TRR mode.

27. The apparatus of claim 16 , further comprising:
row hammer detect logic to detect that access to the target row meets or exceeds the threshold within the time interval.

28. The apparatus of claim 27 , wherein the memory controller comprises the row hammer detect logic.

29. The apparatus of claim 27 , further comprising the DRAM device coupled to the memory controller, wherein the DRAM device comprises the row hammer detect logic.

30. The apparatus of claim 16 , wherein the memory controller comprises an integrated memory controller, integrated with a processor device.

31. A

Assignees

• Intel Corp

Inventors

• Halbert John B
• Bains Kuljit S

Classifications

• G11C11/40603 Primary

  Arbitration, priority and concurrent access to memory cells for read/write or refresh operations · CPC title

• G06F12/0646

  Configuration or reconfiguration · CPC title

• G06F3/0673

  Single storage device · CPC title

• G11C11/40618 Primary

  Refresh operations over multiple banks or interleaving · CPC title

• G06F3/0616

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title