Method, apparatus and system for responding to a row hammer event

Patent metadata

Field	Value
Publication number	US-9564201-B2
Application number	US-201615011286-A
Country	US
Kind code	B2
Filing date	Jan 29, 2016
Priority date	Dec 21, 2012
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.

First claim

What is claimed is:

1. A dynamic random access memory (DRAM) device, comprising:
a bank group, including a target row;
a mode register to store one or more configuration bits to control entry into a targeted row refresh (TRR) mode in response to receipt of a mode register set (MRS) command; and
access logic to receive one or more commands from an associated memory controller, the one or more commands including
a first Activation command to be received when in the TRR mode, the first Activation command directed to the bank group including the target row;
a first Precharge command corresponding to the first Activation command to be received at least a delay of (1.5*tRAS) after the first Activation command, wherein tRAS is a row active timing parameter; and
two additional Activation commands and corresponding additional Precharge commands,

wherein the one or more commands are to refresh at least one victim row physically proximate to the target row.

2. The DRAM device of claim 1 , wherein the mode register comprises Mode Register 2 (MR 2 ).

3. The DRAM device of claim 1 , wherein the access logic is to delay activity within the DRAM device for a mode register set command delay period of tMOD in conjunction with entry into the TRR mode.

4. The DRAM device of claim 1 , further comprising row hammer response logic in the DRAM device, the row hammer response logic to write one or more configuration bits of the mode register to automatically exit the TRR mode after refresh of the at least one victim row.

5. The DRAM device of claim 4 , wherein the row hammer response logic to further count a number of refreshes at the DRAM during TRR mode, and in response to detection of refresh of the at least one victim row, automatically clear the one or more configuration bits from the mode register.

6. The DRAM device of claim 4 , wherein the row hammer response logic to further automatically delay by at least a mode register set command delay period of tMOD in conjunction with automatic exit from the TRR mode.

7. The DRAM device of claim 1 , wherein the DRAM device includes a synchronous DRAM (SDRAM) device compliant with a dual data rate version 4 (DDR4) standard.

8. The DRAM device of claim 1 , further comprising:
row hammer detection logic to determine when the target row has been accessed a threshold number of times within a time interval.

9. The DRAM device of claim 1 , wherein physically proximate comprises physically adjacent.

10. The DRAM device of claim 1 , wherein the memory device is to restrict access commands to activate and precharge commands in the TRR mode.

11. A method at a memory device, comprising:
entering a targeted row refresh (TRR) mode in a dynamic random access memory (DRAM) device in response to receipt of a mode register set (MRS) command;
applying a first Activation command received at the DRAM when in the TRR mode, the first Activation command directed to a bank group including a target row;
applying a Precharge command corresponding to the first Activation command after a delay of at least (1.5*tRAS) after receipt of the first Activation command, wherein tRAS is a row active timing parameter; and
applying two additional Activation commands and corresponding additional Precharge commands,
wherein the Activation commands and corresponding Precharge commands are to refresh at least one victim row physically proximate to the target row.

12. The method of claim 11 , wherein the MRS command comprises an MRS command to set one or more configuration bits of Mode Register 2 (MR 2 ).

13. The method of claim 11 , further comprising:
delaying activity within the DRAM device for a mode register set command delay period of tMOD in conjunction with entry into the TRR mode.

14. The method of claim 11 , further comprising:
writing over the MRS command by the DRAM device to automatically exit the TRR mode after refresh of the at least one victim row.

15. The method of claim 14 , further comprising:
counting a number of refreshes at the DRAM device during TRR mode; and
in response to detecting that the at least one victim row has been refreshed, automatically clearing a TRR mode configuration setting from a mode register set by the MRS command.

16. The method of claim 14 , further comprising:
automatically delaying by at least a mode register set command delay period of tMOD in conjunction with automatically exiting the TRR mode.

17. The method of claim 11 , wherein the DRAM device includes a synchronous DRAM (SDRAM) device compliant with a dual data rate version 4 (DDR4) standard.

18. The method of claim 11 , further comprising:
determining at the DRAM when the target row has been accessed a threshold number of times within a time interval.

19. The method of claim 11 , wherein physically proximate comprises physically adjacent.

20. The method of claim 11 , further comprising:
restricting access commands to activate and precharge commands in the TRR mode.

21. A system, comprising:
a memory controller; and
a dynamic random access memory (DRAM) device including:
a bank group, including a target row; and
a mode register to store one or more configuration bits to control entry into a targeted row refresh (TRR) mode in response to receipt of a mode register set (MRS) command;
wherein the DRAM is to receive one or more commands from the memory controller, including a first Activation command to be received when in the TRR mode, the first Activation command directed to the bank group including the target row; a first Precharge command corresponding to the first Activation command to be received at least a delay of (1.5*tRAS) after the first Activation command, wherein tRAS is a row active timing parameter; and two additional Activation commands and corresponding additional Precharge commands,

wherein the one or more commands are to refresh at least one victim row physically proximate to the target row.

22. The system of claim 21 , wherein the mode register comprises Mode Register 2 (MR 2 ).

23. The system of claim 21 , wherein the DRAM is to delay activity for a mode register set command delay period of tMOD in conjunction with entry into the TRR mode.

24. The system of claim 21 , further comprising row hammer response logic in the DRAM device, the row hammer response logic to write one or more configuration bits of the mode register to automatically exit the TRR mode after refresh of the at least one victim row.

25. The system of claim 24 , wherein the row hammer response logic to further count a number of refreshes at the DRAM during TRR mode, and in response to detection of refresh of the at least one victim row, automatically clear the one or more configuration bits from the mode register.

26. The system of claim 24 , wherein the row hammer response logic to further automatically delay by at least a mode register set command delay period of tMOD in conjunction with automatic exit from the TRR mode.

27. The system of claim 21 , wherein the DRAM device includes a synchronous DRAM (SDRAM) device compliant with a dual data rate version 4 (DDR4) standard.

28. The system of claim 21 , further comprising:
row hammer detection logic to determine when the target row has been accessed a threshold number of times within a time interval.

29. The system of claim 28 , wherein the memory controller comprises the r

Assignees

• Intel Corp

Inventors

• Halbert John B
• Bains Kuljit S

Classifications

• G11C11/40603 Primary

  Arbitration, priority and concurrent access to memory cells for read/write or refresh operations · CPC title

• G11C7/1072

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C11/4063 Primary

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing · CPC title