Method, apparatus and system for responding to a row hammer event

Patent metadata

Field	Value
Publication number	US-9286964-B2
Application number	US-201213725800-A
Country	US
Kind code	B2
Filing date	Dec 21, 2012
Priority date	Dec 21, 2012
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.

First claim

What is claimed is:

1. A memory device comprising:
a first bank including a first row and a second row physically adjacent to the first row;
a second bank, wherein an integrated circuit chip of the memory device includes the first bank and the second bank;
detect logic to configure the memory device in response to an indication that repeated access to the first row exceeds a threshold;
row hammer response logic of the memory device, in response to the indication and prior to receipt of an expected targeted refresh command from an associated memory controller, to restrict access to the first bank for access other than a targeted refresh, to prepare for receipt of the targeted refresh command; and
access logic to service a memory access command from the memory controller prior to receipt of the targeted refresh command, including the access logic to access the second bank in response to the memory access command, the access logic further to perform the targeted refresh of the second row in response to the targeted refresh command received by the memory device from the memory controller after the memory access command.

2. The memory device of claim 1 , wherein the row hammer response logic is to determine address information corresponding to the second row.

3. The memory device of claim 2 , wherein the row hammer response logic to determine address information corresponding to the second row includes the row hammer response logic to determine an offset between logical addresses of physically adjacent rows.

4. The memory device of claim 1 , the detect logic further to maintain a count of a number of accesses to the first bank subsequent to configuration of the memory device, the detect logic further to compare the count to a threshold number.

5. The memory device of claim 4 , wherein the row hammer response logic to enable access to the first bank for access other than the targeted refresh in response to the count exceeding the threshold number.

6. The memory device of claim 1 , further comprising a mode register, wherein the detect logic to configure the memory device includes the detect logic to write to the mode register.

7. The memory device of claim 1 , the row hammer response logic further to signal to the memory controller that repeated access to the first row exceeds the threshold.

8. A method at a memory device by logic of the memory device, the method comprising:
configuring the memory device in response to an indication that repeated access to a first row exceeds a threshold, wherein the memory device comprises:
a first bank including the first row and a second row physically adjacent to the first row; and
a second bank, wherein an integrated circuit chip of the memory device includes the first bank and the second bank;

restricting, in response to the indication and prior to receipt of an expected targeted refresh command from an associated memory controller, access to the first bank for access other than a targeted refresh, to prepare for receipt of the targeted refresh command;
servicing a memory access command from the memory controller prior to receipt of the targeted refresh command, including accessing the second bank in response to the memory access command; and
performing the targeted refresh of the second row in response to the targeted refresh command received by the memory device from the memory controller after the memory access command.

9. The method of claim 8 , further comprising determining address information corresponding to the second row.

10. The method of claim 9 , wherein determining the address information corresponding to the second row includes determining an offset between logical addresses of physically adjacent rows.

11. The method of claim 8 , further comprising: maintaining a count of a number of accesses to the first bank subsequent to configuration of the memory device; and comparing the count to a threshold number.

12. The method of claim 11 , further comprising automatically enabling access to the first bank for access other than the targeted refresh in response to the count exceeding the threshold number.

13. The method of claim 8 , wherein configuring the memory device includes writing to a mode register of the memory device.

14. The method of claim 8 , further comprising signaling the memory controller that repeated access to the first row exceeds the threshold.

15. A memory controller comprising:
detect logic to receive an indication that repeated access to a first row of a memory device exceeds a threshold, wherein the memory device comprises:
a first bank including the first row and a second row physically adjacent to the first row; and
a second bank, wherein an integrated circuit chip of the memory device includes the first bank and the second bank;

command logic to configure the memory device in response to the indication and prior to sending a targeted refresh command for the second row, wherein the memory device, in response to the indication and prior to receipt of the targeted refresh command, to restrict access to the first bank for access other than the targeted refresh to prepare for receipt of the targeted refresh command, the command logic further to send a memory access command prior to the targeted refresh command, wherein the memory device is to access the second bank to service the memory access command, the command logic further to send the targeted refresh command to the memory device after the memory access command is sent, wherein the memory device is to perform the targeted refresh of the second row in response to the targeted refresh command.

16. The memory controller of claim 15 , wherein the indication is based on the memory device identifying the first row as a target of a row hammer event.

17. The memory controller of claim 15 , wherein the the memory device is to determine address information corresponding to the second row.

18. The memory controller of claim 15 , wherein the command logic to configure the memory device including to write to a mode register of the memory device.

19. The memory controller of claim 18 , wherein the command logic to write to the mode register information to identify the first bank for restriction of access to the first bank.

20. A method at a memory controller, the method comprising:
receiving an indication that repeated access to a first row of a memory device exceeds a threshold, wherein the memory device comprises:
a first bank including the first row and a second row physically adjacent to the first row; and
a second bank, wherein an integrated circuit chip of the memory device includes the first bank and the second bank;

configuring the memory device in response to the indication and prior to sending a targeted refresh command for the second row, wherein the memory device, in response to the indication and prior to receipt of the targeted refresh command, to restrict access to the first bank for access other than the targeted refresh to prepare for receipt of the targeted refresh command;
sending a memory access command prior to the targeted refresh command, wherein the memory device is to access the second bank to service the memory access command; and
sending the targeted refresh command to the memory device after the memory access command is sent, wherein the memory device is to perform the targeted refresh of the second row in response to the targeted refresh command.

21. The method of claim 20 , wherein the indication is based on the memory device identifying the fi

Assignees

• Intel Corp

Inventors

• Halbert John B
• Bains Kuljit S

Classifications

• G11C11/40603 Primary

  Arbitration, priority and concurrent access to memory cells for read/write or refresh operations · CPC title

• G11C11/40611

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title

• G06F12/0684

  with feedback, e.g. presence or absence of unit detected by addressing, overflow detection · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title