Semiconductor device

Patent metadata

Field	Value
Publication number	US-9754877-B2
Application number	US-201615242788-A
Country	US
Kind code	B2
Filing date	Aug 22, 2016
Priority date	Aug 26, 2015
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A semiconductor device includes: a semiconductor substrate having a main surface; a first insulating film formed in a convex shape and provided on the main surface of the semiconductor substrate; a first diffusion layer formed on the semiconductor substrate and provided to surround the first insulating film formed in a convex shape, the first diffusion layer being different in conductivity type from the semiconductor substrate; a first conductive layer formed so as to extend across the first insulating film formed in a convex shape, the first conductive layer forming a fuse element; and a second insulating film provided on the first conductive layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate having a main surface;
a first insulating film formed in a convex shape and provided on the main surface of the semiconductor substrate;
a first diffusion layer formed on the semiconductor substrate and provided to surround the first insulating film formed in a convex shape, the first diffusion layer being different in conductivity type from the semiconductor substrate;
a first conductive layer formed so as to extend across the first insulating film formed in a convex shape, the first conductive layer forming a fuse element; and
a second insulating film provided on the first conductive layer;
wherein the semiconductor device includes a power transistor element electrically connected to the first conductive layer.

2. The semiconductor device according to claim 1 , wherein
the power transistor element has a drain or a collector, to which a high voltage is applied, and
the first diffusion layer is set at an electric potential of a ground voltage or about the ground voltage.

3. The semiconductor device according to claim 1 , wherein
the power transistor element includes trench gate electrodes and a second diffusion layer provided between the trench gate electrodes, and
the second diffusion layer and the first diffusion layer are formed in an identical step.

4. The semiconductor device according to claim 3 , further comprising a termination structure including a third insulating film for isolation, wherein
the first insulating film and the third insulating film are formed in an identical step, and
the first insulating film is formed to have a thickness of 300 nm or more.

5. The semiconductor device according to claim 1 , wherein
the power transistor element includes a gate electrode having a second conductive layer, and
the first conductive layer of the fuse element and the second conductive layer of the gate electrode are formed in an identical step.

6. The semiconductor device according to claim 1 , further comprising a termination structure that has a second diffusion layer formed in a ring shape and provided for suppressing an electric field concentration, wherein the second diffusion layer and the first diffusion layer are formed in an identical step.

7. The semiconductor device according to claim 1 ,
wherein the first conductive layer extends across the first insulating film in a first direction, and
wherein the first insulating film formed in a convex shape is formed to have a width of 20 μm or less in the first direction.

8. The semiconductor device according to claim 1 , wherein
the semiconductor device includes a diode element having a second conductive layer, and
the first conductive layer of the fuse element and the second conductive layer of the diode element are formed in an identical step.

9. The semiconductor device according to claim 1 , wherein the first conductive layer of the fuse element includes a prescribed region having a thickness that is adjusted by etching.

10. The semiconductor device according to claim 9 , wherein the prescribed region in the first conductive layer of the fuse element is formed to have a thickness of 200 nm or less.

11. The semiconductor device according to claim 9 , wherein the prescribed region in the first conductive layer of the fuse element is formed on the first insulating film.

12. The semiconductor device according to claim 9 , wherein the first insulating film formed in a convex shape has an end that is removed by the etching.

13. The semiconductor device according to claim 1 , wherein the first conductive layer of the fuse element is formed of a conductive layer intended for the fuse element.

14. The semiconductor device according to claim 1 , wherein the first conductive layer formed on a side surface of the first insulating film formed in a convex shape is greater in width than the first conductive layer formed in a region other than the side surface.

15. The semiconductor device according to claim 1 , further comprising a second conductive layer formed on the second insulating film, wherein
a plurality of the first insulating films each formed in a convex shape is provided,
the first conductive layer is formed so as to extend across the plurality of the first insulating films each formed in a convex shape, and
the second conductive layer and the first conductive layer are connected by a region that is formed on at least one of the plurality of the first insulating films each formed in a convex shape.

16. The semiconductor device according to claim 1 , wherein the fuse element is connected to a non-trimming element formed of a resistor provided based on a path length of the first conductive layer.

17. The semiconductor device according to claim 16 , wherein
the semiconductor device includes a diode element having a second conductive layer, and
a sheet resistance of the first conductive layer and a sheet resistance of the second conductive layer are adjusted in an identical step.

18. A semiconductor device comprising:
a power transistor element; and
a non-trimming element including a fuse element used for adjusting the transistor element,
the fuse element including
a semiconductor substrate having a main surface,
a first insulating film formed in a convex shape and provided on the main surface of the semiconductor substrate,
a first diffusion layer formed on the semiconductor substrate and provided to surround the first insulating film formed in a convex shape, the first diffusion layer being different in conductivity type from the semiconductor substrate,
a first conductive layer formed so as to extend across the first insulating film formed in a convex shape, the first conductive layer forming a fuse element, and
a second insulating film provided on the first conductive layer,

the power transistor element being electrically connected to the first conductive layer and having a drain or a collector, to which a high voltage is applied, and
the first diffusion layer being set at an electric potential of a ground voltage or about the ground voltage.

19. The semiconductor device according to claim 18 , wherein
the non-trimming element includes a second diffusion layer formed on the semiconductor substrate, and
the first diffusion layer and the second diffusion layer are formed in an identical step.

20. A semiconductor device comprising:
a semiconductor substrate having a main surface;
a first insulating film formed in a convex shape and provided on the main surface of the semiconductor substrate;
a first diffusion layer formed on the semiconductor substrate and provided to surround the first insulating film formed in a convex shape, the first diffusion layer being different in conductivity type from the semiconductor substrate;
a first conductive layer formed so as to extend across the first insulating film formed in a convex shape, the first conductive layer forming a fuse element;
a second insulating film provided on the first conductive layer; and
a termination structure that has a second diffusion layer formed in a ring shape and provided for suppressing an electric field concentration, wherein the second diffusion layer and the first diffusion layer are formed in an identical step.

Assignees

• Renesas Electronics Corp

Inventors

• Takahashi Yukio
• Matsuura Hitoshi

Classifications

• H10P74/232

  comprising connection or disconnection of parts of a device in response to a measurement · CPC title

• H10W20/498

  Resistive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/494 Primary

  changeable by the use of an external beam, e.g. laser beam or ion beam · CPC title

• H01L29/7397

  Electricity · mapped topic

• H01L29/0619

  Electricity · mapped topic