Method for forming fuse pad and bond pad of integrated circuit

Patent metadata

Field	Value
Publication number	US-9496221-B2
Application number	US-201213531743-A
Country	US
Kind code	B2
Filing date	Jun 25, 2012
Priority date	Jun 25, 2012
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

The present disclosure relates to a method of fabricating a semiconductor device. A semiconductor device includes a bond pad and a fuse layer. The bond pad includes a coating on an upper surface. A dielectric layer is formed over the bond pad and the fuse layer. A passivation layer is formed over the dielectric layer. An etch is performed to form a bond pad opening and a fuse opening. The etch is performed using only a single mask. The fuse opening defines a fuse window. The upper surface of the bond pad is exposed by substantially removing the coating from the entire upper surface.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor device having a bond pad arranged over a first dielectric layer and a fuse layer arranged within the first dielectric layer;
forming a coating on an upper surface of the bond pad;
forming a second dielectric layer over the bond pad;
performing an etch using a mask to remove a portion of the second dielectric layer to form a bond pad opening and to thin a portion of the first dielectric layer to form a fuse opening, the fuse opening defining a fuse window; and
exposing the upper surface of the bond pad by removing the coating on the upper surface of the bond pad by a solution having an etching selectivity that removes the coating and that does not substantially remove the first dielectric layer;
wherein the second dielectric layer is formed along sidewall and upper surfaces of the bond pad and the coating, and does not overlie the fuse layer prior to performing the etch.

2. The method of claim 1 , wherein forming the coating comprises depositing an anti-reflective coating.

3. The method of claim 1 , wherein forming the coating comprises depositing Titanium-Nitride.

4. The method of claim 1 , wherein exposing the upper surface is performed without a plasma etch.

5. The method of claim 1 , wherein exposing the upper surface is obtained by utilizing the solution that facilitates removal of the coating.

6. The method of claim 5 , wherein the solution includes hydrogen peroxide.

7. The method of claim 1 , further comprising forming a passivation layer over the first dielectric layer.

8. The method of claim 7 , wherein performing the etch comprises etching selected portions of the passivation layer and the first and second dielectric layers.

9. The method of claim 1 , wherein the bond pad comprises a first conductive material and the fuse layer comprises a second conductive material.

10. The method of claim 1 , further comprising forming the mask over the device prior to performing the etch.

11. The method of claim 1 , further comprising removing the mask prior to exposing the upper surface of the bond pad.

12. The method of claim 1 , wherein the etch is selective to the coating and omits etching at least a portion of the coating.

13. A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor device having a bond pad and a fuse layer, the fuse layer surrounded by a first dielectric layer, the bond pad having a coating on an upper surface;
forming a second dielectric layer over the bond pad and the fuse layer;
forming a passivation layer over the second dielectric layer;
forming a mask having a bond pad opening and a fuse opening, the bond pad opening positioned above the bond pad and the fuse opening positioned above the fuse layer;
performing a single etch using the mask to simultaneously expose the coating on the bond pad and to leave a remaining portion of the second dielectric layer on the fuse layer;
removing the mask;
substantially removing the coating to expose the upper surface of the bond pad without leaving coating residue and without removing at least a portion of the remaining portion of the second dielectric layer on the fuse layer; and
removing the passivation layer after removing the coating.

14. The method of claim 13 , wherein the coating is substantially removed by a solution which is selective to the coating.

15. The method of claim 13 , wherein the coating is substantially removed by a solution which includes hydrogen peroxide.

16. The method of claim 13 , wherein performing the single etch comprises etching through portions of the passivation layer defined by the bond pad opening and the fuse opening.

17. A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor device having a first dielectric layer, wherein a first conductive body is arranged over the first dielectric layer and a second conductive body is arranged within the first dielectric layer;
forming a coating on an upper surface of the first conductive body;
forming a second dielectric layer over the first conductive body and the coating;
forming a mask over the first and second dielectric layers, wherein the mask leaves a surface of the second dielectric layer exposed;
performing an etch with the mask in place to remove a portion of the second dielectric layer to expose but not remove the coating on the upper surface of the first conductive body, and to thin a portion of the first dielectric layer over the second conductive body;
removing the mask after the etch; and
removing the coating from the upper surface of the first conductive body;
wherein the second dielectric layer is formed along sidewall and upper surfaces of the first conductive body and the coating, and not extended to overlie the second conductive body prior to performing the etch of the second dielectric layer.

18. The method of claim 17 , wherein the coating on the upper surface of the first conductive body is entirely removed.

19. The method of claim 17 , wherein the coating is removed from the upper surface of the first conductive body while leaving the first dielectric layer un-altered.

20. The method of claim 17 , wherein forming the coating comprises depositing a titanium nitride layer.

Assignees

• Yang Tai-I
• Yang Marcus
• Lin Chih-Hao
• Shue Hong-Seng
• Jang Ruei-Hung
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Tai-I
• Yang Marcus
• Lin Chih-Hao
• Shue Hong-Seng
• Jang Ruei-Hung

Classifications

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/59

  Bond pads specially adapted therefor · CPC title

• H10W72/50

  Bond wires · CPC title

• H10W42/80

  protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W20/494 Primary

  changeable by the use of an external beam, e.g. laser beam or ion beam · CPC title