Timing adjustments across transparent latches to facilitate power reduction

Patent metadata

Field	Value
Publication number	US-9754062-B2
Application number	US-201514934422-A
Country	US
Kind code	B2
Filing date	Nov 6, 2015
Priority date	Nov 6, 2015
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A method of implementing timing adjustments across a transparent latch of an integrated circuit, a system, and a computer program product are described. The method includes obtaining initial input timing slack and input potential power savings at an input and an initial output timing slack and output potential power savings at an output of the transparent latch. The method also includes adjusting a cycle boundary of the transparent latch to obtain a new input timing slack at the input and a new output timing slack at the output of the transparent latch, wherein the new input timing slack is greater than the initial input timing slack based on the input potential power savings being greater than the output potential power savings and the new output timing slack is greater than the initial output timing slack based on the output potential power savings being greater than the input potential power savings.

First claim

What is claimed is:

1. A method of implementing timing adjustments across a transparent latch of an integrated circuit, the method comprising:
obtaining, using a processor, initial input timing slack and input potential power savings at an input of the transparent latch;
obtaining, using the processor, initial output timing slack and output potential power savings at an output of the transparent latch; and
adjusting a cycle boundary of the transparent latch to obtain a new input timing slack at the input of the transparent latch and a new output timing slack at the output of the transparent latch, wherein the cycle boundary is a time period within an active clock interval of the transparent latch, the new input timing slack is greater than the initial input timing slack based on the input potential power savings being greater than the output potential power savings, the new output timing slack is greater than the initial output timing slack based on the output potential power savings being greater than the input potential power savings, and the adjusting the cycle boundary is performed and provided for subsequent manufacturing of the integrated circuit.

2. The method according to claim 1 , wherein the adjusting the cycle boundary includes ensuring that the cycle boundary remains within an active clock duration of the transparent latch.

3. The method according to claim 1 , wherein the adjusting the cycle boundary includes ensuring that the new input timing slack is greater than a threshold input timing slack based on the new input timing slack is less than the initial input timing slack.

4. The method according to claim 1 , wherein the adjusting the cycle boundary includes ensuring that the new output timing slack is greater than a threshold output timing slack based on the new output timing slack is less than the initial output timing slack.

5. The method according to claim 1 , further comprising performing the adjusting the cycle boundary iteratively for each of a set of the transparent latches of the integrated circuit.

6. The method according to claim 1 , wherein the adjusting the cycle boundary is based on a weighting factor, K.

7. The method according to claim 6 , wherein the adjusting the cycle boundary is according to:
(OSin−adjust)−( K *PPSin)==(OSout+adjust)−( K *PPSout), where

OSin is the initial input timing slack, PPSin is the input potential power savings, OSout is the initial output timing slack, PPSout is the output potential power savings, and adjust is a positive or negative integer by which the initial input timing slack and the initial output timing slack are adjusted.

8. The method according to claim 6 , wherein increasing K increases a difference between the initial input timing slack and the new input timing slack and between the initial output timing slack and the new output timing slack.

9. A system to implement timing adjustments across a transparent latch of an integrated circuit, the system comprising:
a memory device configured to store initial input timing slack and input potential power savings at an input of the transparent latch and initial output timing slack and output potential power savings at an output of the transparent latch; and
a processor configured to adjust a cycle boundary of the transparent latch to obtain a new input timing slack at the input of the transparent latch and a new output timing slack at the output of the transparent latch, wherein the cycle boundary is a time period within an active clock interval of the transparent latch, the new input timing slack is greater than the initial input timing slack based on the input potential power savings being greater than the output potential power savings, the new output timing slack is greater than the initial output timing slack based on the output potential power savings being greater than the input potential power savings, and the processor adjusting the cycle boundary is performed and provided for subsequent manufacturing of the integrated circuit.

10. The system according to claim 9 , wherein the processor ensures that the cycle boundary remains within an active clock duration of the transparent latch.

11. The system according to claim 9 , wherein the processor ensures that the new input timing slack is greater than a threshold input timing slack based on the new input timing slack is less than the initial input timing slack, and ensures that the new output timing slack is greater than a threshold output timing slack based on the new output timing slack is less than the initial output timing slack.

12. The system according to claim 9 , wherein the processor adjusts the cycle boundary iteratively for each of a set of the transparent latches of the integrated circuit.

13. The system according to claim 9 , wherein the processor adjusts the cycle boundary based on a weighting factor, K.

14. The system according to claim 13 , wherein the processor adjusts the cycle boundary according to:
(OSin−adjust)−( K *PPSin)==(OSout+adjust)−( K *PPSout), where

OSin is the initial input timing slack, PPSin is the input potential power savings, OSout is the initial output timing slack, PPSout is the output potential power savings, and adjust is a positive or negative integer by which the initial input timing slack and the initial output timing slack are adjusted.

15. The system according to claim 13 , wherein K is input to the processor by a user, and as K increases a difference between the initial input timing slack and the new input timing slack and between the initial output timing slack and the new output timing slack increases.

16. A computer program product for implementing timing adjustments across a transparent latch of an integrated circuit, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to perform a method comprising:
obtaining initial input timing slack and input potential power savings at an input of the transparent latch;
obtaining initial output timing slack and output potential power savings at an output of the transparent latch; and
adjusting a cycle boundary of the transparent latch to obtain a new input timing slack at the input of the transparent latch and a new output timing slack at the output of the transparent latch, wherein the cycle boundary is a time period within an active clock interval of the transparent latch, the new input timing slack is greater than the initial input timing slack based on the input potential power savings being greater than the output potential power savings, the new output timing slack is greater than the initial output timing slack based on the output potential power savings being greater than the input potential power savings, and the adjusting the cycle boundary is performed and provided for subsequent manufacturing of the integrated circuit.

17. The computer program product according to claim 16 , wherein the adjusting the cycle boundary includes ensuring that the cycle boundary remains within an active clock duration of the transparent latch.

18. The computer program product according to claim 16 , wherein the adjusting the cycle boundary includes ensuring that the new input timing slack is greater than a threshold input timing slack based on the new input timing slack is less than the initial input timing slack or ensuring that the new output timing slack is greater than a threshold output timing slack based on the new output timing slack is less than the initial output timing s

Assignees

• IBM

Inventors

• Kalafala Kerim
• Schaeffer Gregory M
• Shuma Stephen G
• Villarrubia Paul G

Classifications

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/35

  Delay-insensitive circuit design, e.g. asynchronous or self-timed · CPC title

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title